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A64: Implement SHA1SU1

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Lioncash 2018-04-13 20:39:25 -04:00 committed by MerryMage
parent 16a001b9ff
commit 205ca6b4cb
2 changed files with 18 additions and 1 deletions
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2
src/frontend/A64/decoder/a64.inc
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@ -330,7 +330,7 @@ INST(SHA1SU0, "SHA1SU0", "01011
//INST(SHA256H2, "SHA256H2", "01011110000mmmmm010100nnnnnddddd") //INST(SHA256H2, "SHA256H2", "01011110000mmmmm010100nnnnnddddd")
//INST(SHA256SU1, "SHA256SU1", "01011110000mmmmm011000nnnnnddddd") //INST(SHA256SU1, "SHA256SU1", "01011110000mmmmm011000nnnnnddddd")
INST(SHA1H, "SHA1H", "0101111000101000000010nnnnnddddd") INST(SHA1H, "SHA1H", "0101111000101000000010nnnnnddddd")
//INST(SHA1SU1, "SHA1SU1", "0101111000101000000110nnnnnddddd") INST(SHA1SU1, "SHA1SU1", "0101111000101000000110nnnnnddddd")
//INST(SHA256SU0, "SHA256SU0", "0101111000101000001010nnnnnddddd") //INST(SHA256SU0, "SHA256SU0", "0101111000101000001010nnnnnddddd")
// Data Processing - FP and SIMD - Scalar copy // Data Processing - FP and SIMD - Scalar copy

17
src/frontend/A64/translate/impl/simd_sha.cpp
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@ -28,6 +28,23 @@ bool TranslatorVisitor::SHA1SU0(Vec Vm, Vec Vn, Vec Vd) {
return true; return true;
} }
bool TranslatorVisitor::SHA1SU1(Vec Vn, Vec Vd) {
const IR::U128 d = ir.GetQ(Vd);
const IR::U128 n = ir.GetQ(Vn);
// Shuffle down the whole vector and zero out the top 32 bits
const IR::U128 shuffled_n = ir.VectorSetElement(32, ir.VectorShuffleWords(n, 0b00111001), 3, ir.Imm32(0));
const IR::U128 t = ir.VectorEor(d, shuffled_n);
const IR::U128 rotated_t = ir.VectorRotateLeft(32, t, 1);
const IR::U32 low_rotated_t = ir.RotateRight(ir.VectorGetElement(32, rotated_t, 0), ir.Imm8(31));
const IR::U32 high_t = ir.VectorGetElement(32, rotated_t, 3);
const IR::U128 result = ir.VectorSetElement(32, rotated_t, 3, ir.Eor(low_rotated_t, high_t));
ir.SetQ(Vd, result);
return true;
}
bool TranslatorVisitor::SHA1H(Vec Vn, Vec Vd) { bool TranslatorVisitor::SHA1H(Vec Vn, Vec Vd) {
const IR::U128 data = ir.GetS(Vn); const IR::U128 data = ir.GetS(Vn);