A64: Implement FCMGT, FCMGE (register) vector double and single precision variants
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350bc70be8
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24e3299276
2 changed files with 43 additions and 13 deletions
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@ -768,7 +768,7 @@ INST(MLS_vec, "MLS (vector)", "0Q101
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//INST(FMLAL_vec_2, "FMLAL, FMLAL2 (vector)", "0Q1011100z1mmmmm110011nnnnnddddd")
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//INST(FADDP_vec_2, "FADDP (vector)", "0Q1011100z1mmmmm110101nnnnnddddd")
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INST(FMUL_vec_2, "FMUL (vector)", "0Q1011100z1mmmmm110111nnnnnddddd")
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//INST(FCMGE_reg_4, "FCMGE (register)", "0Q1011100z1mmmmm111001nnnnnddddd")
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INST(FCMGE_reg_4, "FCMGE (register)", "0Q1011100z1mmmmm111001nnnnnddddd")
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//INST(FACGE_4, "FACGE", "0Q1011100z1mmmmm111011nnnnnddddd")
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//INST(FMAXP_vec_2, "FMAXP (vector)", "0Q1011100z1mmmmm111101nnnnnddddd")
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INST(FDIV_2, "FDIV (vector)", "0Q1011100z1mmmmm111111nnnnnddddd")
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@ -777,7 +777,7 @@ INST(BSL, "BSL", "0Q101
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//INST(FMINNMP_vec_2, "FMINNMP (vector)", "0Q1011101z1mmmmm110001nnnnnddddd")
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//INST(FMLSL_vec_2, "FMLSL, FMLSL2 (vector)", "0Q1011101z1mmmmm110011nnnnnddddd")
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//INST(FABD_4, "FABD", "0Q1011101z1mmmmm110101nnnnnddddd")
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//INST(FCMGT_reg_4, "FCMGT (register)", "0Q1011101z1mmmmm111001nnnnnddddd")
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INST(FCMGT_reg_4, "FCMGT (register)", "0Q1011101z1mmmmm111001nnnnnddddd")
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//INST(FACGT_4, "FACGT", "0Q1011101z1mmmmm111011nnnnnddddd")
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//INST(FMINP_vec_2, "FMINP (vector)", "0Q1011101z1mmmmm111101nnnnnddddd")
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INST(BIT, "BIT", "0Q101110101mmmmm000111nnnnnddddd")
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@ -96,6 +96,40 @@ bool RoundingHalvingAdd(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec V
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v.V(datasize, Vd, result);
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return true;
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}
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enum class ComparisonType {
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EQ,
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GE,
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GT
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};
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bool FPCompareRegister(TranslatorVisitor& v, bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd, ComparisonType type) {
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if (sz && !Q) {
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return v.ReservedValue();
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}
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const size_t esize = sz ? 64 : 32;
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const size_t datasize = Q ? 128 : 64;
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const IR::U128 operand1 = v.V(datasize, Vn);
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const IR::U128 operand2 = v.V(datasize, Vm);
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const IR::U128 result = [&] {
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switch (type) {
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case ComparisonType::EQ:
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return v.ir.FPVectorEqual(esize, operand1, operand2);
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case ComparisonType::GE:
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return v.ir.FPVectorGreaterEqual(esize, operand1, operand2);
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case ComparisonType::GT:
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return v.ir.FPVectorGreater(esize, operand1, operand2);
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}
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UNREACHABLE();
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return IR::U128{};
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}();
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v.V(datasize, Vd, result);
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return true;
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}
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} // Anonymous namespace
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bool TranslatorVisitor::CMGT_reg_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
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@ -345,19 +379,15 @@ bool TranslatorVisitor::FADD_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) {
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}
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bool TranslatorVisitor::FCMEQ_reg_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) {
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if (sz && !Q) {
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return ReservedValue();
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return FPCompareRegister(*this, Q, sz, Vm, Vn, Vd, ComparisonType::EQ);
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}
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const size_t esize = sz ? 64 : 32;
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const size_t datasize = Q ? 128 : 64;
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bool TranslatorVisitor::FCMGE_reg_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) {
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return FPCompareRegister(*this, Q, sz, Vm, Vn, Vd, ComparisonType::GE);
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}
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const IR::U128 operand1 = V(datasize, Vn);
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const IR::U128 operand2 = V(datasize, Vm);
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const IR::U128 result = ir.FPVectorEqual(esize, operand1, operand2);
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V(datasize, Vd, result);
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return true;
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bool TranslatorVisitor::FCMGT_reg_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) {
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return FPCompareRegister(*this, Q, sz, Vm, Vn, Vd, ComparisonType::GT);
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}
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bool TranslatorVisitor::AND_asimd(bool Q, Vec Vm, Vec Vn, Vec Vd) {
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