thumb32: Implement QADD
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cd6e4c7afd
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36fc596a51
4 changed files with 23 additions and 1 deletions
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@ -275,7 +275,7 @@ std::optional<std::reference_wrapper<const Thumb32Matcher<V>>> DecodeThumb32(u32
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//INST(&V::thumb32_UHSUB8, "UHSUB8", "111110101100----1111----0110----"),
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//INST(&V::thumb32_UHSUB8, "UHSUB8", "111110101100----1111----0110----"),
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// Miscellaneous Operations
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// Miscellaneous Operations
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//INST(&V::thumb32_QADD, "QADD", "111110101000----1111----1000----"),
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INST(&V::thumb32_QADD, "QADD", "111110101000nnnn1111dddd1000mmmm"),
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INST(&V::thumb32_QDADD, "QDADD", "111110101000nnnn1111dddd1001mmmm"),
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INST(&V::thumb32_QDADD, "QDADD", "111110101000nnnn1111dddd1001mmmm"),
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INST(&V::thumb32_QSUB, "QSUB", "111110101000nnnn1111dddd1010mmmm"),
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INST(&V::thumb32_QSUB, "QSUB", "111110101000nnnn1111dddd1010mmmm"),
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INST(&V::thumb32_QDSUB, "QDSUB", "111110101000nnnn1111dddd1011mmmm"),
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INST(&V::thumb32_QDSUB, "QDSUB", "111110101000nnnn1111dddd1011mmmm"),
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@ -19,6 +19,20 @@ bool ThumbTranslatorVisitor::thumb32_CLZ(Reg n, Reg d, Reg m) {
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return true;
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return true;
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}
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}
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bool ThumbTranslatorVisitor::thumb32_QADD(Reg n, Reg d, Reg m) {
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if (d == Reg::PC || n == Reg::PC || m == Reg::PC) {
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return UnpredictableInstruction();
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}
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const auto reg_m = ir.GetRegister(m);
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const auto reg_n = ir.GetRegister(n);
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const auto result = ir.SignedSaturatedAdd(reg_m, reg_n);
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ir.SetRegister(d, result.result);
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ir.OrQFlag(result.overflow);
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return true;
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}
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bool ThumbTranslatorVisitor::thumb32_QDADD(Reg n, Reg d, Reg m) {
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bool ThumbTranslatorVisitor::thumb32_QDADD(Reg n, Reg d, Reg m) {
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if (d == Reg::PC || n == Reg::PC || m == Reg::PC) {
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if (d == Reg::PC || n == Reg::PC || m == Reg::PC) {
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return UnpredictableInstruction();
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return UnpredictableInstruction();
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@ -118,6 +118,7 @@ struct ThumbTranslatorVisitor final {
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// thumb32 miscellaneous instructions
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// thumb32 miscellaneous instructions
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bool thumb32_CLZ(Reg n, Reg d, Reg m);
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bool thumb32_CLZ(Reg n, Reg d, Reg m);
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bool thumb32_QADD(Reg n, Reg d, Reg m);
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bool thumb32_QDADD(Reg n, Reg d, Reg m);
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bool thumb32_QDADD(Reg n, Reg d, Reg m);
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bool thumb32_QDSUB(Reg n, Reg d, Reg m);
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bool thumb32_QDSUB(Reg n, Reg d, Reg m);
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bool thumb32_QSUB(Reg n, Reg d, Reg m);
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bool thumb32_QSUB(Reg n, Reg d, Reg m);
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@ -369,6 +369,13 @@ TEST_CASE("Fuzz Thumb32 instructions set", "[JitX64][Thumb][Thumb32]") {
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const auto n = Common::Bits<16, 19>(inst);
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const auto n = Common::Bits<16, 19>(inst);
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return m == n && d != 15 && m != 15;
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return m == n && d != 15 && m != 15;
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}),
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}),
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ThumbInstGen("111110101000nnnn1111dddd1000mmmm", // QADD
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[](u32 inst) {
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const auto d = Common::Bits<8, 11>(inst);
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const auto m = Common::Bits<0, 3>(inst);
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const auto n = Common::Bits<16, 19>(inst);
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return d != 15 && m != 15 && n != 15;
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}),
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ThumbInstGen("111110101000nnnn1111dddd1001mmmm", // QDADD
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ThumbInstGen("111110101000nnnn1111dddd1001mmmm", // QDADD
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[](u32 inst) {
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[](u32 inst) {
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const auto d = Common::Bits<8, 11>(inst);
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const auto d = Common::Bits<8, 11>(inst);
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