mirrors/dynarmic
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

A64: Implement SHA512SU0

Browse source
This commit is contained in:
Lioncash 2018-04-19 13:13:33 -04:00 committed by MerryMage
parent ca903c1585
commit 44d846045a
2 changed files with 25 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
src/frontend/A64/decoder/a64.inc
View file

@ -872,7 +872,7 @@ INST(BCAX, "BCAX", "11001
INST(SM3SS1, "SM3SS1", "11001110010mmmmm0aaaaannnnnddddd")
// Data Processing - FP and SIMD - SHA512 two register
//INST(SHA512SU0, "SHA512SU0", "1100111011000000100000nnnnnddddd")
INST(SHA512SU0, "SHA512SU0", "1100111011000000100000nnnnnddddd")
//INST(SM4E, "SM4E", "1100111011000000100001nnnnnddddd")
// Data Processing - FP and SIMD - Conversion between floating point and fixed point

24
src/frontend/A64/translate/impl/simd_sha512.cpp
View file

@ -8,6 +8,30 @@
namespace Dynarmic::A64 {
bool TranslatorVisitor::SHA512SU0(Vec Vn, Vec Vd) {
const IR::U128 x = ir.GetQ(Vn);
const IR::U128 w = ir.GetQ(Vd);
const auto make_sig = [](IREmitter& ir, IR::U64 data) {
const IR::U64 tmp1 = ir.RotateRight(data, ir.Imm8(1));
const IR::U64 tmp2 = ir.RotateRight(data, ir.Imm8(8));
const IR::U64 tmp3 = ir.LogicalShiftRight(data, ir.Imm8(7));
return ir.Eor(tmp1, ir.Eor(tmp2, tmp3));
};
const IR::U64 lower_x = ir.VectorGetElement(64, x, 0);
const IR::U64 lower_w = ir.VectorGetElement(64, w, 0);
const IR::U64 upper_w = ir.VectorGetElement(64, w, 1);
const IR::U128 low_result = ir.ZeroExtendToQuad(ir.Add(lower_w, make_sig(ir, upper_w)));
const IR::U64 high_result = ir.Add(upper_w, make_sig(ir, lower_x));
const IR::U128 result = ir.VectorSetElement(64, low_result, 1, high_result);
ir.SetQ(Vd, result);
return true;
}
bool TranslatorVisitor::RAX1(Vec Vm, Vec Vn, Vec Vd) {
const IR::U128 m = ir.GetQ(Vm);
const IR::U128 n = ir.GetQ(Vn);