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IR/Value: Rename RegRef and ExtRegRef to A32Reg and A32ExtReg

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This commit is contained in:
MerryMage 2018-01-05 20:30:41 +00:00
parent 83022322d1
commit 44f7f04b5c
5 changed files with 18 additions and 16 deletions
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4
src/frontend/ir/basic_block.cpp
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@ -161,9 +161,9 @@ std::string DumpBlock(const IR::Block& block) {
return fmt::format("#{}", arg.GetU8()); return fmt::format("#{}", arg.GetU8());
case Type::U32: case Type::U32:
return fmt::format("#{:#x}", arg.GetU32()); return fmt::format("#{:#x}", arg.GetU32());
case Type::RegRef: case Type::A32Reg:
return A32::RegToString(arg.GetA32RegRef()); return A32::RegToString(arg.GetA32RegRef());
case Type::ExtRegRef: case Type::A32ExtReg:
return A32::ExtRegToString(arg.GetA32ExtRegRef()); return A32::ExtRegToString(arg.GetA32ExtRegRef());
default: default:
return "<unknown immediate type>"; return "<unknown immediate type>";

4
src/frontend/ir/opcodes.cpp
View file

@ -52,8 +52,8 @@ const char* GetNameOf(Opcode op) {
} }
const char* GetNameOf(Type type) { const char* GetNameOf(Type type) {
static const std::array<const char*, 12> names = { static const std::array<const char*, 14> names = {
"Void", "RegRef", "ExtRegRef", "Opaque", "U1", "U8", "U16", "U32", "U64", "F32", "F64", "CoprocInfo" "Void", "A32Reg", "A32ExtReg", "A64Reg", "A64Vec", "Opaque", "U1", "U8", "U16", "U32", "U64", "F32", "F64", "CoprocInfo"
}; };
return names.at(static_cast<size_t>(type)); return names.at(static_cast<size_t>(type));
} }

6
src/frontend/ir/opcodes.h
View file

@ -31,8 +31,10 @@ constexpr size_t OpcodeCount = static_cast<size_t>(Opcode::NUM_OPCODE);
*/ */
enum class Type { enum class Type {
Void, Void,
RegRef, A32Reg,
ExtRegRef, A32ExtReg,
A64Reg,
A64Vec,
Opaque, Opaque,
U1, U1,
U8, U8,

12
src/frontend/ir/opcodes.inc
View file

@ -5,12 +5,12 @@ OPCODE(Identity, T::Opaque, T::Opaque
OPCODE(Breakpoint, T::Void, ) OPCODE(Breakpoint, T::Void, )
// A32 Context getters/setters // A32 Context getters/setters
A32OPC(GetRegister, T::U32, T::RegRef ) A32OPC(GetRegister, T::U32, T::A32Reg )
A32OPC(GetExtendedRegister32, T::F32, T::ExtRegRef ) A32OPC(GetExtendedRegister32, T::F32, T::A32ExtReg )
A32OPC(GetExtendedRegister64, T::F64, T::ExtRegRef ) A32OPC(GetExtendedRegister64, T::F64, T::A32ExtReg )
A32OPC(SetRegister, T::Void, T::RegRef, T::U32 ) A32OPC(SetRegister, T::Void, T::A32Reg, T::U32 )
A32OPC(SetExtendedRegister32, T::Void, T::ExtRegRef, T::F32 ) A32OPC(SetExtendedRegister32, T::Void, T::A32ExtReg, T::F32 )
A32OPC(SetExtendedRegister64, T::Void, T::ExtRegRef, T::F64 ) A32OPC(SetExtendedRegister64, T::Void, T::A32ExtReg, T::F64 )
A32OPC(GetCpsr, T::U32, ) A32OPC(GetCpsr, T::U32, )
A32OPC(SetCpsr, T::Void, T::U32 ) A32OPC(SetCpsr, T::Void, T::U32 )
A32OPC(SetCpsrNZCV, T::Void, T::U32 ) A32OPC(SetCpsrNZCV, T::Void, T::U32 )

8
src/frontend/ir/value.cpp
View file

@ -15,11 +15,11 @@ Value::Value(Inst* value) : type(Type::Opaque) {
inner.inst = value; inner.inst = value;
} }
Value::Value(A32::Reg value) : type(Type::RegRef) { Value::Value(A32::Reg value) : type(Type::A32Reg) {
inner.imm_a32regref = value; inner.imm_a32regref = value;
} }
Value::Value(A32::ExtReg value) : type(Type::ExtRegRef) { Value::Value(A32::ExtReg value) : type(Type::A32ExtReg) {
inner.imm_a32extregref = value; inner.imm_a32extregref = value;
} }
@ -69,12 +69,12 @@ Type Value::GetType() const {
} }
A32::Reg Value::GetA32RegRef() const { A32::Reg Value::GetA32RegRef() const {
ASSERT(type == Type::RegRef); ASSERT(type == Type::A32Reg);
return inner.imm_a32regref; return inner.imm_a32regref;
} }
A32::ExtReg Value::GetA32ExtRegRef() const { A32::ExtReg Value::GetA32ExtRegRef() const {
ASSERT(type == Type::ExtRegRef); ASSERT(type == Type::A32ExtReg);
return inner.imm_a32extregref; return inner.imm_a32extregref;
} }