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A64: Implement SSRA (scalar)

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Lioncash 2018-04-12 14:39:20 -04:00 committed by MerryMage
parent 255a33936d
commit 52cad2d9d0
2 changed files with 10 additions and 1 deletions
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2
src/frontend/A64/decoder/a64.inc
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@ -468,7 +468,7 @@ INST(SUB_1, "SUB (vector)", "01111
// Data Processing - FP and SIMD - SIMD Scalar shift by immediate // Data Processing - FP and SIMD - SIMD Scalar shift by immediate
INST(SSHR_1, "SSHR", "010111110IIIIiii000001nnnnnddddd") INST(SSHR_1, "SSHR", "010111110IIIIiii000001nnnnnddddd")
//INST(SSRA_1, "SSRA", "010111110IIIIiii000101nnnnnddddd") INST(SSRA_1, "SSRA", "010111110IIIIiii000101nnnnnddddd")
//INST(SRSHR_1, "SRSHR", "010111110IIIIiii001001nnnnnddddd") //INST(SRSHR_1, "SRSHR", "010111110IIIIiii001001nnnnnddddd")
//INST(SRSRA_1, "SRSRA", "010111110IIIIiii001101nnnnnddddd") //INST(SRSRA_1, "SRSRA", "010111110IIIIiii001101nnnnnddddd")
INST(SHL_1, "SHL", "010111110IIIIiii010101nnnnnddddd") INST(SHL_1, "SHL", "010111110IIIIiii010101nnnnnddddd")

9
src/frontend/A64/translate/impl/simd_scalar_shift_by_immediate.cpp
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@ -48,6 +48,15 @@ bool TranslatorVisitor::SSHR_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
return true; return true;
} }
bool TranslatorVisitor::SSRA_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
if (!immh.Bit<3>()) {
return ReservedValue();
}
ShiftRight(*this, immh, immb, Vn, Vd, ShiftExtraBehavior::Accumulate, Signedness::Signed);
return true;
}
bool TranslatorVisitor::SHL_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { bool TranslatorVisitor::SHL_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
if (!immh.Bit<3>()) { if (!immh.Bit<3>()) {
return ReservedValue(); return ReservedValue();