thumb32: Implement SMLAL
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28108c7924
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5859105a61
3 changed files with 24 additions and 1 deletions
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@ -283,7 +283,7 @@ INST(thumb32_SMULL, "SMULL", "111110111000nnnnllllhh
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//INST(thumb32_SDIV, "SDIV", "111110111001------------1111----")
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INST(thumb32_UMULL, "UMULL", "111110111010nnnnllllhhhh0000mmmm")
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//INST(thumb32_UDIV, "UDIV", "111110111011------------1111----")
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//INST(thumb32_SMLAL, "SMLAL", "111110111100------------0000----")
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INST(thumb32_SMLAL, "SMLAL", "111110111100nnnnllllhhhh0000mmmm")
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//INST(thumb32_SMLALXY, "SMLALXY", "111110111100------------10------")
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//INST(thumb32_SMLALD, "SMLALD", "111110111100------------110-----")
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//INST(thumb32_SMLSLD, "SMLSLD", "111110111101------------110-----")
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@ -7,6 +7,28 @@
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namespace Dynarmic::A32 {
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bool ThumbTranslatorVisitor::thumb32_SMLAL(Reg n, Reg dLo, Reg dHi, Reg m) {
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if (dLo == Reg::PC || dHi == Reg::PC || n == Reg::PC || m == Reg::PC) {
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return UnpredictableInstruction();
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}
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if (dHi == dLo) {
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return UnpredictableInstruction();
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}
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const auto n64 = ir.SignExtendWordToLong(ir.GetRegister(n));
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const auto m64 = ir.SignExtendWordToLong(ir.GetRegister(m));
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const auto product = ir.Mul(n64, m64);
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const auto addend = ir.Pack2x32To1x64(ir.GetRegister(dLo), ir.GetRegister(dHi));
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const auto result = ir.Add(product, addend);
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const auto lo = ir.LeastSignificantWord(result);
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const auto hi = ir.MostSignificantWord(result).result;
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ir.SetRegister(dLo, lo);
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ir.SetRegister(dHi, hi);
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return true;
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}
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bool ThumbTranslatorVisitor::thumb32_SMULL(Reg n, Reg dLo, Reg dHi, Reg m) {
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if (dLo == Reg::PC || dHi == Reg::PC || n == Reg::PC || m == Reg::PC) {
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return UnpredictableInstruction();
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@ -117,6 +117,7 @@ struct ThumbTranslatorVisitor final {
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bool thumb32_UDF();
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// thumb32 long multiply, long multiply accumulate, and divide instructions
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bool thumb32_SMLAL(Reg n, Reg dLo, Reg dHi, Reg m);
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bool thumb32_SMULL(Reg n, Reg dLo, Reg dHi, Reg m);
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bool thumb32_UMULL(Reg n, Reg dLo, Reg dHi, Reg m);
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