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A32: Implement ASIMD VRSRA

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Now that we have the accumulation and rounding code in place, VRSRA is
extremely trivial to implement.
This commit is contained in:
Lioncash 2020-06-18 11:03:29 -04:00
parent 14fdd15199
commit 69c999bc66
3 changed files with 7 additions and 1 deletions
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2
src/frontend/A32/decoder/asimd.inc
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@ -61,7 +61,7 @@ INST(asimd_VQSUB, "VQSUB", "1111001U0Dzznnnndddd001
INST(asimd_SHR, "SHR", "1111001U1Diiiiiidddd0000LQM1mmmm") // ASIMD
INST(asimd_SRA, "SRA", "1111001U1Diiiiiidddd0001LQM1mmmm") // ASIMD
INST(asimd_VRSHR, "VRSHR", "1111001U1Diiiiiidddd0010LQM1mmmm") // ASIMD
//INST(asimd_VRSRA, "VRSRA", "1111001U1-vvv-------0011LB-1----") // ASIMD
INST(asimd_VRSRA, "VRSRA", "1111001U1Diiiiiidddd0011LQM1mmmm") // ASIMD
//INST(asimd_VSRI, "VSRI", "111100111-vvv-------0100LB-1----") // ASIMD
//INST(asimd_VSHL, "VSHL", "111100101-vvv-------0101LB-1----") // ASIMD
//INST(asimd_VSLI, "VSLI", "111100111-vvv-------0101LB-1----") // ASIMD

5
src/frontend/A32/translate/impl/asimd_two_regs_shift.cpp
View file

@ -84,4 +84,9 @@ bool ArmTranslatorVisitor::asimd_VRSHR(bool U, bool D, size_t imm6, size_t Vd, b
Accumulating::None, Rounding::Round);
}
bool ArmTranslatorVisitor::asimd_VRSRA(bool U, bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm) {
return ShiftRight(*this, U, D, imm6, Vd, L, Q, M, Vm,
Accumulating::Accumulate, Rounding::Round);
}
} // namespace Dynarmic::A32

1
src/frontend/A32/translate/impl/translate_arm.h
View file

@ -455,6 +455,7 @@ struct ArmTranslatorVisitor final {
bool asimd_SHR(bool U, bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm);
bool asimd_SRA(bool U, bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm);
bool asimd_VRSHR(bool U, bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm);
bool asimd_VRSRA(bool U, bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm);
// Advanced SIMD two register, miscellaneous
bool asimd_VREV(bool D, size_t sz, size_t Vd, size_t op, bool Q, bool M, size_t Vm);