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A64: Implement CMGT (register, scalar)

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Lioncash 2018-04-15 04:56:01 -04:00 committed by MerryMage
parent da6627124b
commit 755981d0da
2 changed files with 17 additions and 1 deletions
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2
src/frontend/A64/decoder/a64.inc
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@ -445,7 +445,7 @@ INST(ADDP_pair, "ADDP (scalar)", "01011
// Data Processing - FP and SIMD - SIMD Scalar three same
//INST(SQADD_1, "SQADD", "01011110zz1mmmmm000011nnnnnddddd")
//INST(SQSUB_1, "SQSUB", "01011110zz1mmmmm001011nnnnnddddd")
//INST(CMGT_reg_1, "CMGT (register)", "01011110zz1mmmmm001101nnnnnddddd")
INST(CMGT_reg_1, "CMGT (register)", "01011110zz1mmmmm001101nnnnnddddd")
//INST(CMGE_reg_1, "CMGE (register)", "01011110zz1mmmmm001111nnnnnddddd")
//INST(SSHL_1, "SSHL", "01011110zz1mmmmm010001nnnnnddddd")
//INST(SQSHL_reg_1, "SQSHL (register)", "01011110zz1mmmmm010011nnnnnddddd")

16
src/frontend/A64/translate/impl/simd_scalar_three_same.cpp
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@ -23,6 +23,22 @@ bool TranslatorVisitor::ADD_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
return true;
}
bool TranslatorVisitor::CMGT_reg_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
if (size != 0b11) {
return ReservedValue();
}
const size_t esize = 8 << size.ZeroExtend();
const size_t datasize = 128;
const IR::U128 operand1 = V(datasize, Vn);
const IR::U128 operand2 = V(datasize, Vm);
const IR::U128 result = ir.VectorGreaterSigned(esize, operand1, operand2);
V_scalar(esize, Vd, ir.VectorGetElement(esize, result, 0));
return true;
}
bool TranslatorVisitor::SUB_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
if (size != 0b11) {
return ReservedValue();