arm_types: Change type signature of operator+ to size_t instead of int
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2 changed files with 8 additions and 8 deletions
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@ -160,17 +160,17 @@ inline size_t RegNumber(ExtReg reg) {
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}
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}
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inline Reg operator+(Reg reg, int number) {
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inline Reg operator+(Reg reg, size_t number) {
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ASSERT(reg != Reg::INVALID_REG);
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int new_reg = static_cast<int>(reg) + number;
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size_t new_reg = static_cast<size_t>(reg) + number;
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ASSERT(new_reg >= 0 && new_reg <= 15);
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return static_cast<Reg>(new_reg);
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}
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inline ExtReg operator+(ExtReg reg, int number) {
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ExtReg new_reg = static_cast<ExtReg>(static_cast<int>(reg) + number);
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inline ExtReg operator+(ExtReg reg, size_t number) {
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ExtReg new_reg = static_cast<ExtReg>(static_cast<size_t>(reg) + number);
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ASSERT((reg >= ExtReg::S0 && reg <= ExtReg::S31 && new_reg >= ExtReg::S0 && new_reg <= ExtReg::S31)
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|| (reg >= ExtReg::D0 && reg <= ExtReg::D31 && new_reg >= ExtReg::D0 && new_reg <= ExtReg::D31));
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@ -362,7 +362,7 @@ bool ArmTranslatorVisitor::vfp2_VSQRT(Cond cond, bool D, size_t Vd, bool sz, boo
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bool ArmTranslatorVisitor::vfp2_VPOP(Cond cond, bool D, size_t Vd, bool sz, Imm8 imm8) {
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const ExtReg d = ToExtReg(sz, Vd, D);
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const unsigned regs = sz ? imm8 >> 1 : imm8;
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const size_t regs = sz ? imm8 >> 1 : imm8;
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if (regs == 0 || RegNumber(d)+regs > 32)
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return UnpredictableInstruction();
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@ -373,7 +373,7 @@ bool ArmTranslatorVisitor::vfp2_VPOP(Cond cond, bool D, size_t Vd, bool sz, Imm8
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if (ConditionPassed(cond)) {
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auto address = ir.GetRegister(Reg::SP);
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for (unsigned i = 0; i < regs; ++i) {
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for (size_t i = 0; i < regs; ++i) {
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if (sz) {
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auto lo = ir.ReadMemory32(address);
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address = ir.Add(address, ir.Imm32(4));
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@ -396,7 +396,7 @@ bool ArmTranslatorVisitor::vfp2_VPOP(Cond cond, bool D, size_t Vd, bool sz, Imm8
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bool ArmTranslatorVisitor::vfp2_VPUSH(Cond cond, bool D, size_t Vd, bool sz, Imm8 imm8) {
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u32 imm32 = imm8 << 2;
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const ExtReg d = ToExtReg(sz, Vd, D);
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const unsigned regs = sz ? imm8 >> 1 : imm8;
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const size_t regs = sz ? imm8 >> 1 : imm8;
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if (regs == 0 || RegNumber(d)+regs > 32)
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return UnpredictableInstruction();
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@ -408,7 +408,7 @@ bool ArmTranslatorVisitor::vfp2_VPUSH(Cond cond, bool D, size_t Vd, bool sz, Imm
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auto address = ir.Sub(ir.GetRegister(Reg::SP), ir.Imm32(imm32));
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ir.SetRegister(Reg::SP, address);
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for (unsigned i = 0; i < regs; ++i) {
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for (size_t i = 0; i < regs; ++i) {
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if (sz) {
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const auto d_u64 = ir.TransferFromFP64(ir.GetExtendedRegister(d + i));
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auto lo = ir.LeastSignificantWord(d_u64);
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