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arm_types: Change type signature of operator+ to size_t instead of int

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This commit is contained in:
MerryMage 2016-08-23 20:07:53 +01:00
parent af9a68f0d1
commit 7a01dba3c4
2 changed files with 8 additions and 8 deletions
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8
src/frontend/arm_types.h
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@ -160,17 +160,17 @@ inline size_t RegNumber(ExtReg reg) {
} }
} }
inline Reg operator+(Reg reg, int number) { inline Reg operator+(Reg reg, size_t number) {
ASSERT(reg != Reg::INVALID_REG); ASSERT(reg != Reg::INVALID_REG);
int new_reg = static_cast<int>(reg) + number; size_t new_reg = static_cast<size_t>(reg) + number;
ASSERT(new_reg >= 0 && new_reg <= 15); ASSERT(new_reg >= 0 && new_reg <= 15);
return static_cast<Reg>(new_reg); return static_cast<Reg>(new_reg);
} }
inline ExtReg operator+(ExtReg reg, int number) { inline ExtReg operator+(ExtReg reg, size_t number) {
ExtReg new_reg = static_cast<ExtReg>(static_cast<int>(reg) + number); ExtReg new_reg = static_cast<ExtReg>(static_cast<size_t>(reg) + number);
ASSERT((reg >= ExtReg::S0 && reg <= ExtReg::S31 && new_reg >= ExtReg::S0 && new_reg <= ExtReg::S31) ASSERT((reg >= ExtReg::S0 && reg <= ExtReg::S31 && new_reg >= ExtReg::S0 && new_reg <= ExtReg::S31)
|| (reg >= ExtReg::D0 && reg <= ExtReg::D31 && new_reg >= ExtReg::D0 && new_reg <= ExtReg::D31)); || (reg >= ExtReg::D0 && reg <= ExtReg::D31 && new_reg >= ExtReg::D0 && new_reg <= ExtReg::D31));

8
src/frontend/translate/translate_arm/vfp2.cpp
View file

@ -362,7 +362,7 @@ bool ArmTranslatorVisitor::vfp2_VSQRT(Cond cond, bool D, size_t Vd, bool sz, boo
bool ArmTranslatorVisitor::vfp2_VPOP(Cond cond, bool D, size_t Vd, bool sz, Imm8 imm8) { bool ArmTranslatorVisitor::vfp2_VPOP(Cond cond, bool D, size_t Vd, bool sz, Imm8 imm8) {
const ExtReg d = ToExtReg(sz, Vd, D); const ExtReg d = ToExtReg(sz, Vd, D);
const unsigned regs = sz ? imm8 >> 1 : imm8; const size_t regs = sz ? imm8 >> 1 : imm8;
if (regs == 0 || RegNumber(d)+regs > 32) if (regs == 0 || RegNumber(d)+regs > 32)
return UnpredictableInstruction(); return UnpredictableInstruction();
@ -373,7 +373,7 @@ bool ArmTranslatorVisitor::vfp2_VPOP(Cond cond, bool D, size_t Vd, bool sz, Imm8
if (ConditionPassed(cond)) { if (ConditionPassed(cond)) {
auto address = ir.GetRegister(Reg::SP); auto address = ir.GetRegister(Reg::SP);
for (unsigned i = 0; i < regs; ++i) { for (size_t i = 0; i < regs; ++i) {
if (sz) { if (sz) {
auto lo = ir.ReadMemory32(address); auto lo = ir.ReadMemory32(address);
address = ir.Add(address, ir.Imm32(4)); address = ir.Add(address, ir.Imm32(4));
@ -396,7 +396,7 @@ bool ArmTranslatorVisitor::vfp2_VPOP(Cond cond, bool D, size_t Vd, bool sz, Imm8
bool ArmTranslatorVisitor::vfp2_VPUSH(Cond cond, bool D, size_t Vd, bool sz, Imm8 imm8) { bool ArmTranslatorVisitor::vfp2_VPUSH(Cond cond, bool D, size_t Vd, bool sz, Imm8 imm8) {
u32 imm32 = imm8 << 2; u32 imm32 = imm8 << 2;
const ExtReg d = ToExtReg(sz, Vd, D); const ExtReg d = ToExtReg(sz, Vd, D);
const unsigned regs = sz ? imm8 >> 1 : imm8; const size_t regs = sz ? imm8 >> 1 : imm8;
if (regs == 0 || RegNumber(d)+regs > 32) if (regs == 0 || RegNumber(d)+regs > 32)
return UnpredictableInstruction(); return UnpredictableInstruction();
@ -408,7 +408,7 @@ bool ArmTranslatorVisitor::vfp2_VPUSH(Cond cond, bool D, size_t Vd, bool sz, Imm
auto address = ir.Sub(ir.GetRegister(Reg::SP), ir.Imm32(imm32)); auto address = ir.Sub(ir.GetRegister(Reg::SP), ir.Imm32(imm32));
ir.SetRegister(Reg::SP, address); ir.SetRegister(Reg::SP, address);
for (unsigned i = 0; i < regs; ++i) { for (size_t i = 0; i < regs; ++i) {
if (sz) { if (sz) {
const auto d_u64 = ir.TransferFromFP64(ir.GetExtendedRegister(d + i)); const auto d_u64 = ir.TransferFromFP64(ir.GetExtendedRegister(d + i));
auto lo = ir.LeastSignificantWord(d_u64); auto lo = ir.LeastSignificantWord(d_u64);