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A64: Implement USHL (scalar)

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Lioncash 2018-04-22 22:45:03 -04:00 committed by MerryMage
parent 41f4717f2b
commit 7efbd73bac
2 changed files with 14 additions and 1 deletions
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2
src/frontend/A64/decoder/a64.inc
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@ -458,7 +458,7 @@ INST(ADD_1, "ADD (vector)", "01011
//INST(UQSUB_1, "UQSUB", "01111110zz1mmmmm001011nnnnnddddd")
INST(CMHI_1, "CMHI (register)", "01111110zz1mmmmm001101nnnnnddddd")
INST(CMHS_1, "CMHS (register)", "01111110zz1mmmmm001111nnnnnddddd")
//INST(USHL_1, "USHL", "01111110zz1mmmmm010001nnnnnddddd")
INST(USHL_1, "USHL", "01111110zz1mmmmm010001nnnnnddddd")
//INST(UQSHL_reg_1, "UQSHL (register)", "01111110zz1mmmmm010011nnnnnddddd")
//INST(URSHL_1, "URSHL", "01111110zz1mmmmm010101nnnnnddddd")
//INST(UQRSHL_1, "UQRSHL", "01111110zz1mmmmm010111nnnnnddddd")

13
src/frontend/A64/translate/impl/simd_scalar_three_same.cpp
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@ -130,4 +130,17 @@ bool TranslatorVisitor::SUB_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
return true;
}
bool TranslatorVisitor::USHL_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
if (size != 0b11) {
return ReservedValue();
}
const IR::U128 operand1 = V(64, Vn);
const IR::U128 operand2 = V(64, Vm);
const IR::U128 result = ir.VectorLogicalVShift(64, operand1, operand2);
V(64, Vd, result);
return true;
}
} // namespace Dynarmic::A64