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thumb32: Implement SSUB16/USUB16

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This commit is contained in:
Lioncash 2021-02-01 16:41:02 -05:00
parent 0e28c63456
commit 8f42fd5c0e
4 changed files with 36 additions and 2 deletions
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4
src/frontend/A32/decoder/thumb32.h
View file

@ -238,7 +238,7 @@ std::optional<std::reference_wrapper<const Thumb32Matcher<V>>> DecodeThumb32(u32
INST(&V::thumb32_SADD16, "SADD16", "111110101001nnnn1111dddd0000mmmm"), INST(&V::thumb32_SADD16, "SADD16", "111110101001nnnn1111dddd0000mmmm"),
INST(&V::thumb32_SASX, "SASX", "111110101010nnnn1111dddd0000mmmm"), INST(&V::thumb32_SASX, "SASX", "111110101010nnnn1111dddd0000mmmm"),
INST(&V::thumb32_SSAX, "SSAX", "111110101110nnnn1111dddd0000mmmm"), INST(&V::thumb32_SSAX, "SSAX", "111110101110nnnn1111dddd0000mmmm"),
//INST(&V::thumb32_SSUB16, "SSUB16", "111110101101----1111----0000----"), INST(&V::thumb32_SSUB16, "SSUB16", "111110101101nnnn1111dddd0000mmmm"),
//INST(&V::thumb32_SADD8, "SADD8", "111110101000----1111----0000----"), //INST(&V::thumb32_SADD8, "SADD8", "111110101000----1111----0000----"),
//INST(&V::thumb32_SSUB8, "SSUB8", "111110101100----1111----0000----"), //INST(&V::thumb32_SSUB8, "SSUB8", "111110101100----1111----0000----"),
//INST(&V::thumb32_QADD16, "QADD16", "111110101001----1111----0001----"), //INST(&V::thumb32_QADD16, "QADD16", "111110101001----1111----0001----"),
@ -258,7 +258,7 @@ std::optional<std::reference_wrapper<const Thumb32Matcher<V>>> DecodeThumb32(u32
INST(&V::thumb32_UADD16, "UADD16", "111110101001nnnn1111dddd0100mmmm"), INST(&V::thumb32_UADD16, "UADD16", "111110101001nnnn1111dddd0100mmmm"),
INST(&V::thumb32_UASX, "UASX", "111110101010nnnn1111dddd0100mmmm"), INST(&V::thumb32_UASX, "UASX", "111110101010nnnn1111dddd0100mmmm"),
INST(&V::thumb32_USAX, "USAX", "111110101110nnnn1111dddd0100mmmm"), INST(&V::thumb32_USAX, "USAX", "111110101110nnnn1111dddd0100mmmm"),
//INST(&V::thumb32_USUB16, "USUB16", "111110101101----1111----0100----"), INST(&V::thumb32_USUB16, "USUB16", "111110101101nnnn1111dddd0100mmmm"),
//INST(&V::thumb32_UADD8, "UADD8", "111110101000----1111----0100----"), //INST(&V::thumb32_UADD8, "UADD8", "111110101000----1111----0100----"),
//INST(&V::thumb32_USUB8, "USUB8", "111110101100----1111----0100----"), //INST(&V::thumb32_USUB8, "USUB8", "111110101100----1111----0100----"),
//INST(&V::thumb32_UQADD16, "UQADD16", "111110101001----1111----0101----"), //INST(&V::thumb32_UQADD16, "UQADD16", "111110101001----1111----0101----"),

28
src/frontend/A32/translate/impl/thumb32_parallel.cpp
View file

@ -49,6 +49,20 @@ bool ThumbTranslatorVisitor::thumb32_SSAX(Reg n, Reg d, Reg m) {
return true; return true;
} }
bool ThumbTranslatorVisitor::thumb32_SSUB16(Reg n, Reg d, Reg m) {
if (d == Reg::PC || n == Reg::PC || m == Reg::PC) {
return UnpredictableInstruction();
}
const auto reg_m = ir.GetRegister(m);
const auto reg_n = ir.GetRegister(n);
const auto result = ir.PackedSubS16(reg_n, reg_m);
ir.SetRegister(d, result.result);
ir.SetGEFlags(result.ge);
return true;
}
bool ThumbTranslatorVisitor::thumb32_UADD16(Reg n, Reg d, Reg m) { bool ThumbTranslatorVisitor::thumb32_UADD16(Reg n, Reg d, Reg m) {
if (d == Reg::PC || n == Reg::PC || m == Reg::PC) { if (d == Reg::PC || n == Reg::PC || m == Reg::PC) {
return UnpredictableInstruction(); return UnpredictableInstruction();
@ -91,4 +105,18 @@ bool ThumbTranslatorVisitor::thumb32_USAX(Reg n, Reg d, Reg m) {
return true; return true;
} }
bool ThumbTranslatorVisitor::thumb32_USUB16(Reg n, Reg d, Reg m) {
if (d == Reg::PC || n == Reg::PC || m == Reg::PC) {
return UnpredictableInstruction();
}
const auto reg_m = ir.GetRegister(m);
const auto reg_n = ir.GetRegister(n);
const auto result = ir.PackedSubU16(reg_n, reg_m);
ir.SetRegister(d, result.result);
ir.SetGEFlags(result.ge);
return true;
}
} // namespace Dynarmic::A32 } // namespace Dynarmic::A32

2
src/frontend/A32/translate/impl/translate_thumb.h
View file

@ -132,9 +132,11 @@ struct ThumbTranslatorVisitor final {
bool thumb32_SADD16(Reg n, Reg d, Reg m); bool thumb32_SADD16(Reg n, Reg d, Reg m);
bool thumb32_SASX(Reg n, Reg d, Reg m); bool thumb32_SASX(Reg n, Reg d, Reg m);
bool thumb32_SSAX(Reg n, Reg d, Reg m); bool thumb32_SSAX(Reg n, Reg d, Reg m);
bool thumb32_SSUB16(Reg n, Reg d, Reg m);
bool thumb32_UADD16(Reg n, Reg d, Reg m); bool thumb32_UADD16(Reg n, Reg d, Reg m);
bool thumb32_UASX(Reg n, Reg d, Reg m); bool thumb32_UASX(Reg n, Reg d, Reg m);
bool thumb32_USAX(Reg n, Reg d, Reg m); bool thumb32_USAX(Reg n, Reg d, Reg m);
bool thumb32_USUB16(Reg n, Reg d, Reg m);
}; };
} // namespace Dynarmic::A32 } // namespace Dynarmic::A32

4
tests/A32/fuzz_thumb.cpp
View file

@ -420,12 +420,16 @@ TEST_CASE("Fuzz Thumb32 instructions set", "[JitX64][Thumb][Thumb32]") {
three_reg_not_r15), three_reg_not_r15),
ThumbInstGen("111110101110nnnn1111dddd0000mmmm", // SSAX ThumbInstGen("111110101110nnnn1111dddd0000mmmm", // SSAX
three_reg_not_r15), three_reg_not_r15),
ThumbInstGen("111110101101nnnn1111dddd0000mmmm", // SSUB16
three_reg_not_r15),
ThumbInstGen("111110101001nnnn1111dddd0100mmmm", // UADD16 ThumbInstGen("111110101001nnnn1111dddd0100mmmm", // UADD16
three_reg_not_r15), three_reg_not_r15),
ThumbInstGen("111110101010nnnn1111dddd0100mmmm", // UASX ThumbInstGen("111110101010nnnn1111dddd0100mmmm", // UASX
three_reg_not_r15), three_reg_not_r15),
ThumbInstGen("111110101110nnnn1111dddd0100mmmm", // USAX ThumbInstGen("111110101110nnnn1111dddd0100mmmm", // USAX
three_reg_not_r15), three_reg_not_r15),
ThumbInstGen("111110101101nnnn1111dddd0100mmmm", // USUB16
three_reg_not_r15),
}; };
const auto instruction_select = [&]() -> u32 { const auto instruction_select = [&]() -> u32 {