A64: Implement FNMADD
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2 changed files with 15 additions and 1 deletions
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@ -941,5 +941,5 @@ INST(FCSEL_float, "FCSEL", "00011
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// Data Processing - FP and SIMD - Floating point data processing three register
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// Data Processing - FP and SIMD - Floating point data processing three register
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INST(FMADD_float, "FMADD", "00011111yy0mmmmm0aaaaannnnnddddd")
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INST(FMADD_float, "FMADD", "00011111yy0mmmmm0aaaaannnnnddddd")
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INST(FMSUB_float, "FMSUB", "00011111yy0mmmmm1aaaaannnnnddddd")
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INST(FMSUB_float, "FMSUB", "00011111yy0mmmmm1aaaaannnnnddddd")
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//INST(FNMADD_float, "FNMADD", "00011111yy1mmmmm0aaaaannnnnddddd")
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INST(FNMADD_float, "FNMADD", "00011111yy1mmmmm0aaaaannnnnddddd")
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//INST(FNMSUB_float, "FNMSUB", "00011111yy1mmmmm1aaaaannnnnddddd")
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//INST(FNMSUB_float, "FNMSUB", "00011111yy1mmmmm1aaaaannnnnddddd")
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@ -51,4 +51,18 @@ bool TranslatorVisitor::FMSUB_float(Imm<2> type, Vec Vm, Vec Va, Vec Vn, Vec Vd)
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return true;
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return true;
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}
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}
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bool TranslatorVisitor::FNMADD_float(Imm<2> type, Vec Vm, Vec Va, Vec Vn, Vec Vd) {
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const auto datasize = GetDataSize(type);
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if (!datasize || *datasize == 16) {
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return UnallocatedEncoding();
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}
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const IR::U32U64 operanda = V_scalar(*datasize, Va);
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const IR::U32U64 operand1 = V_scalar(*datasize, Vn);
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const IR::U32U64 operand2 = V_scalar(*datasize, Vm);
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const IR::U32U64 result = ir.FPMulAdd(ir.FPNeg(operanda), ir.FPNeg(operand1), operand2, true);
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V_scalar(*datasize, Vd, result);
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return true;
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}
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} // namespace Dynarmic::A64
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} // namespace Dynarmic::A64
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