A64: Implement CMGT (register)
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2 changed files with 13 additions and 1 deletions
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@ -707,7 +707,7 @@ INST(NOT, "NOT", "0Q101
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//INST(SRHADD, "SRHADD", "0Q001110zz1mmmmm000101nnnnnddddd")
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//INST(SHSUB, "SHSUB", "0Q001110zz1mmmmm001001nnnnnddddd")
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//INST(SQSUB_2, "SQSUB", "0Q001110zz1mmmmm001011nnnnnddddd")
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//INST(CMGT_reg_2, "CMGT (register)", "0Q001110zz1mmmmm001101nnnnnddddd")
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INST(CMGT_reg_2, "CMGT (register)", "0Q001110zz1mmmmm001101nnnnnddddd")
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//INST(CMGE_reg_2, "CMGE (register)", "0Q001110zz1mmmmm001111nnnnnddddd")
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//INST(SSHL_2, "SSHL", "0Q001110zz1mmmmm010001nnnnnddddd")
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//INST(SQSHL_reg_2, "SQSHL (register)", "0Q001110zz1mmmmm010011nnnnnddddd")
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@ -8,6 +8,18 @@
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namespace Dynarmic::A64 {
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bool TranslatorVisitor::CMGT_reg_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
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if (size == 0b11 && !Q) return ReservedValue();
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const size_t esize = 8 << size.ZeroExtend<size_t>();
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const size_t datasize = Q ? 128 : 64;
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const IR::U128 operand1 = V(datasize, Vn);
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const IR::U128 operand2 = V(datasize, Vm);
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const IR::U128 result = ir.VectorGreaterSigned(esize, operand1, operand2);
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V(datasize, Vd, result);
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return true;
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}
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bool TranslatorVisitor::ADD_vector(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
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if (size == 0b11 && !Q) return ReservedValue();
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const size_t esize = 8 << size.ZeroExtend<size_t>();
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