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A64: Implement FADD (vector), vector variant

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This commit is contained in:
MerryMage 2018-02-11 16:30:03 +00:00
parent 98c8e7d1af
commit aed4fd3ec3
2 changed files with 15 additions and 1 deletions
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2
src/frontend/A64/decoder/a64.inc
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@ -716,7 +716,7 @@ INST(MUL_vec, "MUL (vector)", "0Q001
INST(ADDP_vec, "ADDP (vector)", "0Q001110zz1mmmmm101111nnnnnddddd")
//INST(FMAXNM_2, "FMAXNM (vector)", "0Q0011100z1mmmmm110001nnnnnddddd")
//INST(FMLA_vec_2, "FMLA (vector)", "0Q0011100z1mmmmm110011nnnnnddddd")
//INST(FADD_2, "FADD (vector)", "0Q0011100z1mmmmm110101nnnnnddddd")
INST(FADD_2, "FADD (vector)", "0Q0011100z1mmmmm110101nnnnnddddd")
//INST(FMAX_2, "FMAX (vector)", "0Q0011100z1mmmmm111101nnnnnddddd")
//INST(FMULX_vec_4, "FMULX", "0Q0011100z1mmmmm110111nnnnnddddd")
//INST(FCMEQ_reg_4, "FCMEQ (register)", "0Q0011100z1mmmmm111001nnnnnddddd")

14
src/frontend/A64/translate/impl/simd_three_same.cpp
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@ -69,6 +69,20 @@ bool TranslatorVisitor::ADDP_vec(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
return true;
}
bool TranslatorVisitor::FADD_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) {
if (sz && !Q) {
return ReservedValue();
}
const size_t esize = sz ? 64 : 32;
const size_t datasize = Q ? 128 : 64;
const IR::U128 operand1 = V(datasize, Vn);
const IR::U128 operand2 = V(datasize, Vm);
const IR::U128 result = ir.FPVectorAdd(esize, operand1, operand2);
V(datasize, Vd, result);
return true;
}
bool TranslatorVisitor::AND_asimd(bool Q, Vec Vm, Vec Vn, Vec Vd) {
const size_t datasize = Q ? 128 : 64;