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frontend/ir_emitter: Add half-precision opcode for FPMulAdd

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Lioncash 2019-04-13 00:12:25 -04:00 committed by MerryMage
parent 79a892d23c
commit bd82513199
6 changed files with 57 additions and 42 deletions
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6
src/backend/x64/emit_x64_floating_point.cpp
View file

@ -608,6 +608,7 @@ template<size_t fsize>
static void EmitFPMulAdd(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) { static void EmitFPMulAdd(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) {
using FPT = mp::unsigned_integer_of_size<fsize>; using FPT = mp::unsigned_integer_of_size<fsize>;
if constexpr (fsize != 16) {
if (code.DoesCpuSupport(Xbyak::util::Cpu::tFMA)) { if (code.DoesCpuSupport(Xbyak::util::Cpu::tFMA)) {
auto args = ctx.reg_alloc.GetArgumentInfo(inst); auto args = ctx.reg_alloc.GetArgumentInfo(inst);
@ -657,6 +658,7 @@ static void EmitFPMulAdd(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) {
ctx.reg_alloc.DefineValue(inst, result); ctx.reg_alloc.DefineValue(inst, result);
return; return;
} }
}
auto args = ctx.reg_alloc.GetArgumentInfo(inst); auto args = ctx.reg_alloc.GetArgumentInfo(inst);
ctx.reg_alloc.HostCall(inst, args[0], args[1], args[2]); ctx.reg_alloc.HostCall(inst, args[0], args[1], args[2]);
@ -673,6 +675,10 @@ static void EmitFPMulAdd(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) {
#endif #endif
} }
void EmitX64::EmitFPMulAdd16(EmitContext& ctx, IR::Inst* inst) {
EmitFPMulAdd<16>(code, ctx, inst);
}
void EmitX64::EmitFPMulAdd32(EmitContext& ctx, IR::Inst* inst) { void EmitX64::EmitFPMulAdd32(EmitContext& ctx, IR::Inst* inst) {
EmitFPMulAdd<32>(code, ctx, inst); EmitFPMulAdd<32>(code, ctx, inst);
} }

2
src/frontend/A64/translate/impl/simd_scalar_x_indexed_element.cpp
View file

@ -36,7 +36,7 @@ bool MultiplyByElement(TranslatorVisitor& v, bool sz, Imm<1> L, Imm<1> M, Imm<4>
const size_t esize = sz ? 64 : 32; const size_t esize = sz ? 64 : 32;
const IR::U32U64 element = v.ir.VectorGetElement(esize, v.V(idxdsize, Vm), index); const IR::U32U64 element = v.ir.VectorGetElement(esize, v.V(idxdsize, Vm), index);
const IR::U32U64 result = [&] { const IR::U32U64 result = [&]() -> IR::U32U64 {
IR::U32U64 operand1 = v.V_scalar(esize, Vn); IR::U32U64 operand1 = v.V_scalar(esize, Vn);
if (extra_behavior == ExtraBehavior::None) { if (extra_behavior == ExtraBehavior::None) {

13
src/frontend/ir/ir_emitter.cpp
View file

@ -1867,13 +1867,20 @@ U32U64 IREmitter::FPMul(const U32U64& a, const U32U64& b, bool fpcr_controlled)
} }
} }
U32U64 IREmitter::FPMulAdd(const U32U64& a, const U32U64& b, const U32U64& c, bool fpcr_controlled) { U16U32U64 IREmitter::FPMulAdd(const U16U32U64& a, const U16U32U64& b, const U16U32U64& c, bool fpcr_controlled) {
ASSERT(fpcr_controlled); ASSERT(fpcr_controlled);
ASSERT(a.GetType() == b.GetType()); ASSERT(a.GetType() == b.GetType());
if (a.GetType() == Type::U32) {
switch (a.GetType()) {
case Type::U16:
return Inst<U16>(Opcode::FPMulAdd16, a, b, c);
case Type::U32:
return Inst<U32>(Opcode::FPMulAdd32, a, b, c); return Inst<U32>(Opcode::FPMulAdd32, a, b, c);
} else { case Type::U64:
return Inst<U64>(Opcode::FPMulAdd64, a, b, c); return Inst<U64>(Opcode::FPMulAdd64, a, b, c);
default:
UNREACHABLE();
return U16U32U64{};
} }
} }

2
src/frontend/ir/ir_emitter.h
View file

@ -301,7 +301,7 @@ public:
U32U64 FPMin(const U32U64& a, const U32U64& b, bool fpcr_controlled); U32U64 FPMin(const U32U64& a, const U32U64& b, bool fpcr_controlled);
U32U64 FPMinNumeric(const U32U64& a, const U32U64& b, bool fpcr_controlled); U32U64 FPMinNumeric(const U32U64& a, const U32U64& b, bool fpcr_controlled);
U32U64 FPMul(const U32U64& a, const U32U64& b, bool fpcr_controlled); U32U64 FPMul(const U32U64& a, const U32U64& b, bool fpcr_controlled);
U32U64 FPMulAdd(const U32U64& addend, const U32U64& op1, const U32U64& op2, bool fpcr_controlled); U16U32U64 FPMulAdd(const U16U32U64& addend, const U16U32U64& op1, const U16U32U64& op2, bool fpcr_controlled);
U32U64 FPMulX(const U32U64& a, const U32U64& b); U32U64 FPMulX(const U32U64& a, const U32U64& b);
U16U32U64 FPNeg(const U16U32U64& a); U16U32U64 FPNeg(const U16U32U64& a);
U32U64 FPRecipEstimate(const U32U64& a); U32U64 FPRecipEstimate(const U32U64& a);

1
src/frontend/ir/microinstruction.cpp
View file

@ -269,6 +269,7 @@ bool Inst::ReadsFromAndWritesToFPSRCumulativeExceptionBits() const {
case Opcode::FPMinNumeric64: case Opcode::FPMinNumeric64:
case Opcode::FPMul32: case Opcode::FPMul32:
case Opcode::FPMul64: case Opcode::FPMul64:
case Opcode::FPMulAdd16:
case Opcode::FPMulAdd32: case Opcode::FPMulAdd32:
case Opcode::FPMulAdd64: case Opcode::FPMulAdd64:
case Opcode::FPRecipEstimate32: case Opcode::FPRecipEstimate32:

1
src/frontend/ir/opcodes.inc
View file

@ -479,6 +479,7 @@ OPCODE(FPMinNumeric32, U32, U32,
OPCODE(FPMinNumeric64, U64, U64, U64 ) OPCODE(FPMinNumeric64, U64, U64, U64 )
OPCODE(FPMul32, U32, U32, U32 ) OPCODE(FPMul32, U32, U32, U32 )
OPCODE(FPMul64, U64, U64, U64 ) OPCODE(FPMul64, U64, U64, U64 )
OPCODE(FPMulAdd16, U16, U16, U16, U16 )
OPCODE(FPMulAdd32, U32, U32, U32, U32 ) OPCODE(FPMulAdd32, U32, U32, U32, U32 )
OPCODE(FPMulAdd64, U64, U64, U64, U64 ) OPCODE(FPMulAdd64, U64, U64, U64, U64 )
OPCODE(FPMulX32, U32, U32, U32 ) OPCODE(FPMulX32, U32, U32, U32 )