frontend/ir_emitter: Add half-precision opcode for FPMulAdd
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parent
79a892d23c
commit
bd82513199
6 changed files with 57 additions and 42 deletions
src
backend/x64
frontend
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@ -608,54 +608,56 @@ template<size_t fsize>
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static void EmitFPMulAdd(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) {
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static void EmitFPMulAdd(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) {
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using FPT = mp::unsigned_integer_of_size<fsize>;
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using FPT = mp::unsigned_integer_of_size<fsize>;
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tFMA)) {
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if constexpr (fsize != 16) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tFMA)) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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Xbyak::Label end, fallback;
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Xbyak::Label end, fallback;
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const Xbyak::Xmm operand1 = ctx.reg_alloc.UseXmm(args[0]);
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const Xbyak::Xmm operand1 = ctx.reg_alloc.UseXmm(args[0]);
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const Xbyak::Xmm operand2 = ctx.reg_alloc.UseXmm(args[1]);
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const Xbyak::Xmm operand2 = ctx.reg_alloc.UseXmm(args[1]);
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const Xbyak::Xmm operand3 = ctx.reg_alloc.UseXmm(args[2]);
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const Xbyak::Xmm operand3 = ctx.reg_alloc.UseXmm(args[2]);
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const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm();
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const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm();
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const Xbyak::Xmm tmp = ctx.reg_alloc.ScratchXmm();
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const Xbyak::Xmm tmp = ctx.reg_alloc.ScratchXmm();
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code.movaps(result, operand1);
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code.movaps(result, operand1);
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FCODE(vfmadd231s)(result, operand2, operand3);
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FCODE(vfmadd231s)(result, operand2, operand3);
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code.movaps(tmp, code.MConst(xword, fsize == 32 ? f32_non_sign_mask : f64_non_sign_mask));
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code.movaps(tmp, code.MConst(xword, fsize == 32 ? f32_non_sign_mask : f64_non_sign_mask));
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code.andps(tmp, result);
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code.andps(tmp, result);
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FCODE(ucomis)(tmp, code.MConst(xword, fsize == 32 ? f32_smallest_normal : f64_smallest_normal));
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FCODE(ucomis)(tmp, code.MConst(xword, fsize == 32 ? f32_smallest_normal : f64_smallest_normal));
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code.jz(fallback, code.T_NEAR);
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code.jz(fallback, code.T_NEAR);
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code.L(end);
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code.L(end);
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code.SwitchToFarCode();
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code.SwitchToFarCode();
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code.L(fallback);
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code.L(fallback);
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code.sub(rsp, 8);
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code.sub(rsp, 8);
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ABI_PushCallerSaveRegistersAndAdjustStackExcept(code, HostLocXmmIdx(result.getIdx()));
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ABI_PushCallerSaveRegistersAndAdjustStackExcept(code, HostLocXmmIdx(result.getIdx()));
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code.movq(code.ABI_PARAM1, operand1);
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code.movq(code.ABI_PARAM1, operand1);
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code.movq(code.ABI_PARAM2, operand2);
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code.movq(code.ABI_PARAM2, operand2);
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code.movq(code.ABI_PARAM3, operand3);
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code.movq(code.ABI_PARAM3, operand3);
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code.mov(code.ABI_PARAM4.cvt32(), ctx.FPCR().Value());
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code.mov(code.ABI_PARAM4.cvt32(), ctx.FPCR().Value());
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#ifdef _WIN32
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#ifdef _WIN32
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code.sub(rsp, 16 + ABI_SHADOW_SPACE);
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code.sub(rsp, 16 + ABI_SHADOW_SPACE);
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code.lea(rax, code.ptr[code.r15 + code.GetJitStateInfo().offsetof_fpsr_exc]);
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code.lea(rax, code.ptr[code.r15 + code.GetJitStateInfo().offsetof_fpsr_exc]);
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code.mov(qword[rsp + ABI_SHADOW_SPACE], rax);
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code.mov(qword[rsp + ABI_SHADOW_SPACE], rax);
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code.CallFunction(&FP::FPMulAdd<FPT>);
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code.CallFunction(&FP::FPMulAdd<FPT>);
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code.add(rsp, 16 + ABI_SHADOW_SPACE);
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code.add(rsp, 16 + ABI_SHADOW_SPACE);
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#else
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#else
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code.lea(code.ABI_PARAM5, code.ptr[code.r15 + code.GetJitStateInfo().offsetof_fpsr_exc]);
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code.lea(code.ABI_PARAM5, code.ptr[code.r15 + code.GetJitStateInfo().offsetof_fpsr_exc]);
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code.CallFunction(&FP::FPMulAdd<FPT>);
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code.CallFunction(&FP::FPMulAdd<FPT>);
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#endif
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#endif
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code.movq(result, code.ABI_RETURN);
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code.movq(result, code.ABI_RETURN);
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ABI_PopCallerSaveRegistersAndAdjustStackExcept(code, HostLocXmmIdx(result.getIdx()));
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ABI_PopCallerSaveRegistersAndAdjustStackExcept(code, HostLocXmmIdx(result.getIdx()));
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code.add(rsp, 8);
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code.add(rsp, 8);
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code.jmp(end, code.T_NEAR);
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code.jmp(end, code.T_NEAR);
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code.SwitchToNearCode();
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code.SwitchToNearCode();
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ctx.reg_alloc.DefineValue(inst, result);
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ctx.reg_alloc.DefineValue(inst, result);
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return;
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return;
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}
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}
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}
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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@ -673,6 +675,10 @@ static void EmitFPMulAdd(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) {
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#endif
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#endif
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}
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}
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void EmitX64::EmitFPMulAdd16(EmitContext& ctx, IR::Inst* inst) {
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EmitFPMulAdd<16>(code, ctx, inst);
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}
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void EmitX64::EmitFPMulAdd32(EmitContext& ctx, IR::Inst* inst) {
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void EmitX64::EmitFPMulAdd32(EmitContext& ctx, IR::Inst* inst) {
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EmitFPMulAdd<32>(code, ctx, inst);
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EmitFPMulAdd<32>(code, ctx, inst);
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}
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}
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@ -36,7 +36,7 @@ bool MultiplyByElement(TranslatorVisitor& v, bool sz, Imm<1> L, Imm<1> M, Imm<4>
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const size_t esize = sz ? 64 : 32;
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const size_t esize = sz ? 64 : 32;
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const IR::U32U64 element = v.ir.VectorGetElement(esize, v.V(idxdsize, Vm), index);
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const IR::U32U64 element = v.ir.VectorGetElement(esize, v.V(idxdsize, Vm), index);
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const IR::U32U64 result = [&] {
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const IR::U32U64 result = [&]() -> IR::U32U64 {
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IR::U32U64 operand1 = v.V_scalar(esize, Vn);
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IR::U32U64 operand1 = v.V_scalar(esize, Vn);
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if (extra_behavior == ExtraBehavior::None) {
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if (extra_behavior == ExtraBehavior::None) {
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@ -1867,13 +1867,20 @@ U32U64 IREmitter::FPMul(const U32U64& a, const U32U64& b, bool fpcr_controlled)
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}
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}
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}
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}
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U32U64 IREmitter::FPMulAdd(const U32U64& a, const U32U64& b, const U32U64& c, bool fpcr_controlled) {
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U16U32U64 IREmitter::FPMulAdd(const U16U32U64& a, const U16U32U64& b, const U16U32U64& c, bool fpcr_controlled) {
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ASSERT(fpcr_controlled);
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ASSERT(fpcr_controlled);
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ASSERT(a.GetType() == b.GetType());
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ASSERT(a.GetType() == b.GetType());
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if (a.GetType() == Type::U32) {
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switch (a.GetType()) {
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case Type::U16:
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return Inst<U16>(Opcode::FPMulAdd16, a, b, c);
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case Type::U32:
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return Inst<U32>(Opcode::FPMulAdd32, a, b, c);
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return Inst<U32>(Opcode::FPMulAdd32, a, b, c);
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} else {
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case Type::U64:
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return Inst<U64>(Opcode::FPMulAdd64, a, b, c);
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return Inst<U64>(Opcode::FPMulAdd64, a, b, c);
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default:
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UNREACHABLE();
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return U16U32U64{};
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}
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}
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}
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}
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@ -301,7 +301,7 @@ public:
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U32U64 FPMin(const U32U64& a, const U32U64& b, bool fpcr_controlled);
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U32U64 FPMin(const U32U64& a, const U32U64& b, bool fpcr_controlled);
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U32U64 FPMinNumeric(const U32U64& a, const U32U64& b, bool fpcr_controlled);
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U32U64 FPMinNumeric(const U32U64& a, const U32U64& b, bool fpcr_controlled);
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U32U64 FPMul(const U32U64& a, const U32U64& b, bool fpcr_controlled);
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U32U64 FPMul(const U32U64& a, const U32U64& b, bool fpcr_controlled);
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U32U64 FPMulAdd(const U32U64& addend, const U32U64& op1, const U32U64& op2, bool fpcr_controlled);
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U16U32U64 FPMulAdd(const U16U32U64& addend, const U16U32U64& op1, const U16U32U64& op2, bool fpcr_controlled);
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U32U64 FPMulX(const U32U64& a, const U32U64& b);
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U32U64 FPMulX(const U32U64& a, const U32U64& b);
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U16U32U64 FPNeg(const U16U32U64& a);
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U16U32U64 FPNeg(const U16U32U64& a);
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U32U64 FPRecipEstimate(const U32U64& a);
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U32U64 FPRecipEstimate(const U32U64& a);
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@ -269,6 +269,7 @@ bool Inst::ReadsFromAndWritesToFPSRCumulativeExceptionBits() const {
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case Opcode::FPMinNumeric64:
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case Opcode::FPMinNumeric64:
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case Opcode::FPMul32:
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case Opcode::FPMul32:
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case Opcode::FPMul64:
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case Opcode::FPMul64:
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case Opcode::FPMulAdd16:
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case Opcode::FPMulAdd32:
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case Opcode::FPMulAdd32:
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case Opcode::FPMulAdd64:
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case Opcode::FPMulAdd64:
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case Opcode::FPRecipEstimate32:
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case Opcode::FPRecipEstimate32:
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@ -479,6 +479,7 @@ OPCODE(FPMinNumeric32, U32, U32,
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OPCODE(FPMinNumeric64, U64, U64, U64 )
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OPCODE(FPMinNumeric64, U64, U64, U64 )
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OPCODE(FPMul32, U32, U32, U32 )
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OPCODE(FPMul32, U32, U32, U32 )
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OPCODE(FPMul64, U64, U64, U64 )
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OPCODE(FPMul64, U64, U64, U64 )
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OPCODE(FPMulAdd16, U16, U16, U16, U16 )
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OPCODE(FPMulAdd32, U32, U32, U32, U32 )
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OPCODE(FPMulAdd32, U32, U32, U32, U32 )
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OPCODE(FPMulAdd64, U64, U64, U64, U64 )
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OPCODE(FPMulAdd64, U64, U64, U64, U64 )
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OPCODE(FPMulX32, U32, U32, U32 )
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OPCODE(FPMulX32, U32, U32, U32 )
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