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frontend/ir/ir_emitter: Amend FPRecipExponent to handle half-precision floating point

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This commit is contained in:
Lioncash 2019-03-09 17:36:00 -05:00 committed by MerryMage
parent 974fbf0677
commit bd892ec4ef
5 changed files with 17 additions and 4 deletions
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4
src/backend/x64/emit_x64_floating_point.cpp
View file

@ -728,6 +728,10 @@ static void EmitFPRecipExponent(BlockOfCode& code, EmitContext& ctx, IR::Inst* i
code.CallFunction(&FP::FPRecipExponent<FPT>);
}
void EmitX64::EmitFPRecipExponent16(EmitContext& ctx, IR::Inst* inst) {
EmitFPRecipExponent<u16>(code, ctx, inst);
}
void EmitX64::EmitFPRecipExponent32(EmitContext& ctx, IR::Inst* inst) {
EmitFPRecipExponent<u32>(code, ctx, inst);
}

13
src/frontend/ir/ir_emitter.cpp
View file

@ -1895,11 +1895,18 @@ U32U64 IREmitter::FPRecipEstimate(const U32U64& a) {
return Inst<U64>(Opcode::FPRecipEstimate64, a);
}
U32U64 IREmitter::FPRecipExponent(const U32U64& a) {
if (a.GetType() == Type::U32) {
U16U32U64 IREmitter::FPRecipExponent(const U16U32U64& a) {
switch (a.GetType()) {
case Type::U16:
return Inst<U16>(Opcode::FPRecipExponent16, a);
case Type::U32:
return Inst<U32>(Opcode::FPRecipExponent32, a);
case Type::U64:
return Inst<U64>(Opcode::FPRecipExponent64, a);
default:
UNREACHABLE();
return U16U32U64{};
}
return Inst<U64>(Opcode::FPRecipExponent64, a);
}
U32U64 IREmitter::FPRecipStepFused(const U32U64& a, const U32U64& b) {

2
src/frontend/ir/ir_emitter.h
View file

@ -305,7 +305,7 @@ public:
U32U64 FPMulX(const U32U64& a, const U32U64& b);
U32U64 FPNeg(const U32U64& a);
U32U64 FPRecipEstimate(const U32U64& a);
U32U64 FPRecipExponent(const U32U64& a);
U16U32U64 FPRecipExponent(const U16U32U64& a);
U32U64 FPRecipStepFused(const U32U64& a, const U32U64& b);
U32U64 FPRoundInt(const U32U64& a, FP::RoundingMode rounding, bool exact);
U32U64 FPRSqrtEstimate(const U32U64& a);

1
src/frontend/ir/microinstruction.cpp
View file

@ -273,6 +273,7 @@ bool Inst::ReadsFromAndWritesToFPSRCumulativeExceptionBits() const {
case Opcode::FPMulAdd64:
case Opcode::FPRecipEstimate32:
case Opcode::FPRecipEstimate64:
case Opcode::FPRecipExponent16:
case Opcode::FPRecipExponent32:
case Opcode::FPRecipExponent64:
case Opcode::FPRecipStepFused32:

1
src/frontend/ir/opcodes.inc
View file

@ -486,6 +486,7 @@ OPCODE(FPNeg32, U32, U32
OPCODE(FPNeg64, U64, U64 )
OPCODE(FPRecipEstimate32, U32, U32 )
OPCODE(FPRecipEstimate64, U64, U64 )
OPCODE(FPRecipExponent16, U16, U16 )
OPCODE(FPRecipExponent32, U32, U32 )
OPCODE(FPRecipExponent64, U64, U64 )
OPCODE(FPRecipStepFused32, U32, U32, U32 )