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translate_arm/exception_generating: Invert conditionals where applicable

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Lioncash 2019-03-01 00:22:45 -05:00 committed by MerryMage
parent d8a8d3b073
commit c2de6ecfd0
1 changed files with 18 additions and 14 deletions
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32
src/frontend/A32/translate/translate_arm/exception_generating.cpp
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@ -10,33 +10,37 @@
namespace Dynarmic::A32 {
// BKPT #<imm16>
bool ArmTranslatorVisitor::arm_BKPT(Cond cond, Imm12 /*imm12*/, Imm4 /*imm4*/) {
if (cond != Cond::AL && !options.define_unpredictable_behaviour) {
return UnpredictableInstruction();
}
// UNPREDICTABLE: The instruction executes conditionally.
if (ConditionPassed(cond)) {
ir.ExceptionRaised(Exception::Breakpoint);
ir.SetTerm(IR::Term::CheckHalt{IR::Term::ReturnToDispatch{}});
return false;
if (!ConditionPassed(cond)) {
return true;
}
return true;
ir.ExceptionRaised(Exception::Breakpoint);
ir.SetTerm(IR::Term::CheckHalt{IR::Term::ReturnToDispatch{}});
return false;
}
// SVC<c> #<imm24>
bool ArmTranslatorVisitor::arm_SVC(Cond cond, Imm24 imm24) {
u32 imm32 = imm24;
// SVC<c> #<imm24>
if (ConditionPassed(cond)) {
ir.PushRSB(ir.current_location.AdvancePC(4));
ir.BranchWritePC(ir.Imm32(ir.current_location.PC() + 4));
ir.CallSupervisor(ir.Imm32(imm32));
ir.SetTerm(IR::Term::CheckHalt{IR::Term::PopRSBHint{}});
return false;
if (!ConditionPassed(cond)) {
return true;
}
return true;
const u32 imm32 = imm24;
ir.PushRSB(ir.current_location.AdvancePC(4));
ir.BranchWritePC(ir.Imm32(ir.current_location.PC() + 4));
ir.CallSupervisor(ir.Imm32(imm32));
ir.SetTerm(IR::Term::CheckHalt{IR::Term::PopRSBHint{}});
return false;
}
// UDF<c> #<imm16>
bool ArmTranslatorVisitor::arm_UDF() {
return UndefinedInstruction();
}