translate_arm/exception_generating: Invert conditionals where applicable
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1 changed files with 18 additions and 14 deletions
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@ -10,33 +10,37 @@
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namespace Dynarmic::A32 {
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namespace Dynarmic::A32 {
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// BKPT #<imm16>
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bool ArmTranslatorVisitor::arm_BKPT(Cond cond, Imm12 /*imm12*/, Imm4 /*imm4*/) {
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bool ArmTranslatorVisitor::arm_BKPT(Cond cond, Imm12 /*imm12*/, Imm4 /*imm4*/) {
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if (cond != Cond::AL && !options.define_unpredictable_behaviour) {
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if (cond != Cond::AL && !options.define_unpredictable_behaviour) {
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return UnpredictableInstruction();
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return UnpredictableInstruction();
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}
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}
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// UNPREDICTABLE: The instruction executes conditionally.
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// UNPREDICTABLE: The instruction executes conditionally.
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if (ConditionPassed(cond)) {
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if (!ConditionPassed(cond)) {
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ir.ExceptionRaised(Exception::Breakpoint);
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return true;
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ir.SetTerm(IR::Term::CheckHalt{IR::Term::ReturnToDispatch{}});
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return false;
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}
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}
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return true;
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ir.ExceptionRaised(Exception::Breakpoint);
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ir.SetTerm(IR::Term::CheckHalt{IR::Term::ReturnToDispatch{}});
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return false;
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}
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}
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// SVC<c> #<imm24>
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bool ArmTranslatorVisitor::arm_SVC(Cond cond, Imm24 imm24) {
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bool ArmTranslatorVisitor::arm_SVC(Cond cond, Imm24 imm24) {
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u32 imm32 = imm24;
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if (!ConditionPassed(cond)) {
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// SVC<c> #<imm24>
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return true;
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if (ConditionPassed(cond)) {
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ir.PushRSB(ir.current_location.AdvancePC(4));
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ir.BranchWritePC(ir.Imm32(ir.current_location.PC() + 4));
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ir.CallSupervisor(ir.Imm32(imm32));
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ir.SetTerm(IR::Term::CheckHalt{IR::Term::PopRSBHint{}});
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return false;
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}
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}
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return true;
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const u32 imm32 = imm24;
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ir.PushRSB(ir.current_location.AdvancePC(4));
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ir.BranchWritePC(ir.Imm32(ir.current_location.PC() + 4));
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ir.CallSupervisor(ir.Imm32(imm32));
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ir.SetTerm(IR::Term::CheckHalt{IR::Term::PopRSBHint{}});
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return false;
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}
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}
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// UDF<c> #<imm16>
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bool ArmTranslatorVisitor::arm_UDF() {
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bool ArmTranslatorVisitor::arm_UDF() {
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return UndefinedInstruction();
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return UndefinedInstruction();
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}
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}
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