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IR: Rename PackedAbsDiffSumS8 to PackedAbsDiffSumU8

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Merry 2022-07-30 12:24:17 +01:00 • committed by merry
parent ee2bc92993
commit cd537dc711
7 changed files with 11 additions and 11 deletions
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4
src/dynarmic/backend/arm64/emit_arm64_packed.cpp
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@ -382,10 +382,10 @@ void EmitIR<IR::Opcode::PackedSaturatedSubS16>(oaknut::CodeGenerator& code, Emit
} }
template<> template<>
void EmitIR<IR::Opcode::PackedAbsDiffSumS8>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) { void EmitIR<IR::Opcode::PackedAbsDiffSumU8>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
EmitPackedOp(code, ctx, inst, [&](auto& Vresult, auto& Va, auto& Vb) { EmitPackedOp(code, ctx, inst, [&](auto& Vresult, auto& Va, auto& Vb) {
code.MOVI(D2, oaknut::RepImm{0b00001111}); code.MOVI(D2, oaknut::RepImm{0b00001111});
code.SABD(Vresult->B8(), Va->B8(), Vb->B8()); code.UABD(Vresult->B8(), Va->B8(), Vb->B8());
code.AND(Vresult->B8(), Vresult->B8(), V2.B8()); // TODO: Zext tracking code.AND(Vresult->B8(), Vresult->B8(), V2.B8()); // TODO: Zext tracking
code.UADDLV(Vresult->toH(), Vresult->B8()); code.UADDLV(Vresult->toH(), Vresult->B8());
}); });

2
src/dynarmic/backend/x64/emit_x64_packed.cpp
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@ -646,7 +646,7 @@ void EmitX64::EmitPackedSaturatedSubS16(EmitContext& ctx, IR::Inst* inst) {
EmitPackedOperation(code, ctx, inst, &Xbyak::CodeGenerator::psubsw); EmitPackedOperation(code, ctx, inst, &Xbyak::CodeGenerator::psubsw);
} }
void EmitX64::EmitPackedAbsDiffSumS8(EmitContext& ctx, IR::Inst* inst) { void EmitX64::EmitPackedAbsDiffSumU8(EmitContext& ctx, IR::Inst* inst) {
auto args = ctx.reg_alloc.GetArgumentInfo(inst); auto args = ctx.reg_alloc.GetArgumentInfo(inst);
const Xbyak::Xmm xmm_a = ctx.reg_alloc.UseScratchXmm(args[0]); const Xbyak::Xmm xmm_a = ctx.reg_alloc.UseScratchXmm(args[0]);

4
src/dynarmic/frontend/A32/translate/impl/parallel.cpp
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@ -177,7 +177,7 @@ bool TranslatorVisitor::arm_USAD8(Cond cond, Reg d, Reg m, Reg n) {
return true; return true;
} }
const auto result = ir.PackedAbsDiffSumS8(ir.GetRegister(n), ir.GetRegister(m)); const auto result = ir.PackedAbsDiffSumU8(ir.GetRegister(n), ir.GetRegister(m));
ir.SetRegister(d, result); ir.SetRegister(d, result);
return true; return true;
} }
@ -192,7 +192,7 @@ bool TranslatorVisitor::arm_USADA8(Cond cond, Reg d, Reg a, Reg m, Reg n) {
return true; return true;
} }
const auto tmp = ir.PackedAbsDiffSumS8(ir.GetRegister(n), ir.GetRegister(m)); const auto tmp = ir.PackedAbsDiffSumU8(ir.GetRegister(n), ir.GetRegister(m));
const auto result = ir.AddWithCarry(ir.GetRegister(a), tmp, ir.Imm1(0)); const auto result = ir.AddWithCarry(ir.GetRegister(a), tmp, ir.Imm1(0));
ir.SetRegister(d, result); ir.SetRegister(d, result);
return true; return true;

4
src/dynarmic/frontend/A32/translate/impl/thumb32_multiply.cpp
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@ -288,7 +288,7 @@ bool TranslatorVisitor::thumb32_USAD8(Reg n, Reg d, Reg m) {
const auto reg_m = ir.GetRegister(m); const auto reg_m = ir.GetRegister(m);
const auto reg_n = ir.GetRegister(n); const auto reg_n = ir.GetRegister(n);
const auto result = ir.PackedAbsDiffSumS8(reg_n, reg_m); const auto result = ir.PackedAbsDiffSumU8(reg_n, reg_m);
ir.SetRegister(d, result); ir.SetRegister(d, result);
return true; return true;
@ -302,7 +302,7 @@ bool TranslatorVisitor::thumb32_USADA8(Reg n, Reg a, Reg d, Reg m) {
const auto reg_a = ir.GetRegister(a); const auto reg_a = ir.GetRegister(a);
const auto reg_m = ir.GetRegister(m); const auto reg_m = ir.GetRegister(m);
const auto reg_n = ir.GetRegister(n); const auto reg_n = ir.GetRegister(n);
const auto tmp = ir.PackedAbsDiffSumS8(reg_n, reg_m); const auto tmp = ir.PackedAbsDiffSumU8(reg_n, reg_m);
const auto result = ir.AddWithCarry(reg_a, tmp, ir.Imm1(0)); const auto result = ir.AddWithCarry(reg_a, tmp, ir.Imm1(0));
ir.SetRegister(d, result); ir.SetRegister(d, result);

4
src/dynarmic/ir/ir_emitter.cpp
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@ -848,8 +848,8 @@ U32 IREmitter::PackedSaturatedSubS16(const U32& a, const U32& b) {
return Inst<U32>(Opcode::PackedSaturatedSubS16, a, b); return Inst<U32>(Opcode::PackedSaturatedSubS16, a, b);
} }
U32 IREmitter::PackedAbsDiffSumS8(const U32& a, const U32& b) { U32 IREmitter::PackedAbsDiffSumU8(const U32& a, const U32& b) {
return Inst<U32>(Opcode::PackedAbsDiffSumS8, a, b); return Inst<U32>(Opcode::PackedAbsDiffSumU8, a, b);
} }
U32 IREmitter::PackedSelect(const U32& ge, const U32& a, const U32& b) { U32 IREmitter::PackedSelect(const U32& ge, const U32& a, const U32& b) {

2
src/dynarmic/ir/ir_emitter.h
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@ -195,7 +195,7 @@ public:
U32 PackedSaturatedAddS16(const U32& a, const U32& b); U32 PackedSaturatedAddS16(const U32& a, const U32& b);
U32 PackedSaturatedSubU16(const U32& a, const U32& b); U32 PackedSaturatedSubU16(const U32& a, const U32& b);
U32 PackedSaturatedSubS16(const U32& a, const U32& b); U32 PackedSaturatedSubS16(const U32& a, const U32& b);
U32 PackedAbsDiffSumS8(const U32& a, const U32& b); U32 PackedAbsDiffSumU8(const U32& a, const U32& b);
U32 PackedSelect(const U32& ge, const U32& a, const U32& b); U32 PackedSelect(const U32& ge, const U32& a, const U32& b);
U32 CRC32Castagnoli8(const U32& a, const U32& b); U32 CRC32Castagnoli8(const U32& a, const U32& b);

2
src/dynarmic/ir/opcodes.inc
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@ -250,7 +250,7 @@ OPCODE(PackedSaturatedAddU16, U32, U32,
OPCODE(PackedSaturatedAddS16, U32, U32, U32 ) OPCODE(PackedSaturatedAddS16, U32, U32, U32 )
OPCODE(PackedSaturatedSubU16, U32, U32, U32 ) OPCODE(PackedSaturatedSubU16, U32, U32, U32 )
OPCODE(PackedSaturatedSubS16, U32, U32, U32 ) OPCODE(PackedSaturatedSubS16, U32, U32, U32 )
OPCODE(PackedAbsDiffSumS8, U32, U32, U32 ) OPCODE(PackedAbsDiffSumU8, U32, U32, U32 )
OPCODE(PackedSelect, U32, U32, U32, U32 ) OPCODE(PackedSelect, U32, U32, U32, U32 )
// CRC instructions // CRC instructions