thumb32: Implement RBIT
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e2bc7eeb93
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cee31c5274
4 changed files with 34 additions and 1 deletions
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@ -281,7 +281,7 @@ std::optional<std::reference_wrapper<const Thumb32Matcher<V>>> DecodeThumb32(u32
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//INST(&V::thumb32_QDSUB, "QDSUB", "111110101000----1111----1011----"),
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//INST(&V::thumb32_REV, "REV", "111110101001----1111----1000----"),
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//INST(&V::thumb32_REV16, "REV16", "111110101001----1111----1001----"),
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//INST(&V::thumb32_RBIT, "RBIT", "111110101001----1111----1010----"),
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INST(&V::thumb32_RBIT, "RBIT", "111110101001nnnn1111dddd1010mmmm"),
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INST(&V::thumb32_REVSH, "REVSH", "111110101001nnnn1111dddd1011mmmm"),
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INST(&V::thumb32_SEL, "SEL", "111110101010nnnn1111dddd1000mmmm"),
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INST(&V::thumb32_CLZ, "CLZ", "111110101011nnnn1111dddd1000mmmm"),
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@ -19,6 +19,31 @@ bool ThumbTranslatorVisitor::thumb32_CLZ(Reg n, Reg d, Reg m) {
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return true;
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}
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bool ThumbTranslatorVisitor::thumb32_RBIT(Reg n, Reg d, Reg m) {
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if (m != n || d == Reg::PC || m == Reg::PC) {
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return UnpredictableInstruction();
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}
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const IR::U32 swapped = ir.ByteReverseWord(ir.GetRegister(m));
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// ((x & 0xF0F0F0F0) >> 4) | ((x & 0x0F0F0F0F) << 4)
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const IR::U32 first_lsr = ir.LogicalShiftRight(ir.And(swapped, ir.Imm32(0xF0F0F0F0)), ir.Imm8(4));
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const IR::U32 first_lsl = ir.LogicalShiftLeft(ir.And(swapped, ir.Imm32(0x0F0F0F0F)), ir.Imm8(4));
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const IR::U32 corrected = ir.Or(first_lsl, first_lsr);
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// ((x & 0x88888888) >> 3) | ((x & 0x44444444) >> 1) |
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// ((x & 0x22222222) << 1) | ((x & 0x11111111) << 3)
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const IR::U32 second_lsr = ir.LogicalShiftRight(ir.And(corrected, ir.Imm32(0x88888888)), ir.Imm8(3));
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const IR::U32 third_lsr = ir.LogicalShiftRight(ir.And(corrected, ir.Imm32(0x44444444)), ir.Imm8(1));
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const IR::U32 second_lsl = ir.LogicalShiftLeft(ir.And(corrected, ir.Imm32(0x22222222)), ir.Imm8(1));
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const IR::U32 third_lsl = ir.LogicalShiftLeft(ir.And(corrected, ir.Imm32(0x11111111)), ir.Imm8(3));
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const IR::U32 result = ir.Or(ir.Or(ir.Or(second_lsr, third_lsr), second_lsl), third_lsl);
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ir.SetRegister(d, result);
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return true;
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}
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bool ThumbTranslatorVisitor::thumb32_REVSH(Reg n, Reg d, Reg m) {
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if (m != n || d == Reg::PC || m == Reg::PC) {
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return UnpredictableInstruction();
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@ -118,6 +118,7 @@ struct ThumbTranslatorVisitor final {
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// thumb32 miscellaneous instructions
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bool thumb32_CLZ(Reg n, Reg d, Reg m);
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bool thumb32_RBIT(Reg n, Reg d, Reg m);
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bool thumb32_REVSH(Reg n, Reg d, Reg m);
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bool thumb32_SEL(Reg n, Reg d, Reg m);
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};
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@ -369,6 +369,13 @@ TEST_CASE("Fuzz Thumb32 instructions set", "[JitX64][Thumb][Thumb32]") {
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const auto n = Common::Bits<16, 19>(inst);
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return m == n && d != 15 && m != 15;
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}),
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ThumbInstGen("111110101001nnnn1111dddd1010mmmm", // RBIT
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[](u32 inst) {
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const auto d = Common::Bits<8, 11>(inst);
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const auto m = Common::Bits<0, 3>(inst);
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const auto n = Common::Bits<16, 19>(inst);
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return m == n && d != 15 && m != 15;
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}),
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ThumbInstGen("111110101001nnnn1111dddd1011mmmm", // REVSH
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[](u32 inst) {
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const auto d = Common::Bits<8, 11>(inst);
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