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A64: Handle S32->F32 case for SCVTF (vector)

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Lioncash 2018-04-19 15:24:08 -04:00 committed by MerryMage
parent 38fa984b53
commit d1f5b084b4
2 changed files with 20 additions and 1 deletions
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2
src/frontend/A64/decoder/a64.inc
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@ -592,7 +592,7 @@ INST(XTN, "XTN, XTN2", "0Q001
//INST(FCVTAS_3, "FCVTAS (vector)", "0Q00111001111001110010nnnnnddddd")
//INST(FCVTAS_4, "FCVTAS (vector)", "0Q0011100z100001110010nnnnnddddd")
//INST(SCVTF_int_3, "SCVTF (vector, integer)", "0Q00111001111001110110nnnnnddddd")
//INST(SCVTF_int_4, "SCVTF (vector, integer)", "0Q0011100z100001110110nnnnnddddd")
INST(SCVTF_int_4, "SCVTF (vector, integer)", "0Q0011100z100001110110nnnnnddddd")
//INST(FCMGT_zero_3, "FCMGT (zero)", "0Q00111011111000110010nnnnnddddd")
//INST(FCMGT_zero_4, "FCMGT (zero)", "0Q0011101z100000110010nnnnnddddd")
//INST(FCMEQ_zero_3, "FCMEQ (zero)", "0Q00111011111000110110nnnnnddddd")

19
src/frontend/A64/translate/impl/simd_two_register_misc.cpp
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@ -243,4 +243,23 @@ bool TranslatorVisitor::REV64_asimd(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
return true;
}
bool TranslatorVisitor::SCVTF_int_4(bool Q, bool sz, Vec Vn, Vec Vd) {
if (sz && !Q) {
return ReservedValue();
}
if (sz) {
// TODO: Implement
return InterpretThisInstruction();
}
const size_t datasize = Q ? 128 : 64;
const IR::U128 operand = V(datasize, Vn);
const IR::U128 result = ir.FPVectorS32ToSingle(operand);
V(datasize, Vd, result);
return true;
}
} // namespace Dynarmic::A64