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A64: Implement CMGE (register)

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This commit is contained in:
MerryMage 2018-02-13 18:29:54 +00:00
parent 9d85991906
commit d5af052f06
2 changed files with 13 additions and 1 deletions
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2
src/frontend/A64/decoder/a64.inc
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@ -708,7 +708,7 @@ INST(NOT, "NOT", "0Q101
//INST(SHSUB, "SHSUB", "0Q001110zz1mmmmm001001nnnnnddddd") //INST(SHSUB, "SHSUB", "0Q001110zz1mmmmm001001nnnnnddddd")
//INST(SQSUB_2, "SQSUB", "0Q001110zz1mmmmm001011nnnnnddddd") //INST(SQSUB_2, "SQSUB", "0Q001110zz1mmmmm001011nnnnnddddd")
INST(CMGT_reg_2, "CMGT (register)", "0Q001110zz1mmmmm001101nnnnnddddd") INST(CMGT_reg_2, "CMGT (register)", "0Q001110zz1mmmmm001101nnnnnddddd")
//INST(CMGE_reg_2, "CMGE (register)", "0Q001110zz1mmmmm001111nnnnnddddd") INST(CMGE_reg_2, "CMGE (register)", "0Q001110zz1mmmmm001111nnnnnddddd")
//INST(SSHL_2, "SSHL", "0Q001110zz1mmmmm010001nnnnnddddd") //INST(SSHL_2, "SSHL", "0Q001110zz1mmmmm010001nnnnnddddd")
//INST(SQSHL_reg_2, "SQSHL (register)", "0Q001110zz1mmmmm010011nnnnnddddd") //INST(SQSHL_reg_2, "SQSHL (register)", "0Q001110zz1mmmmm010011nnnnnddddd")
//INST(SRSHL_2, "SRSHL", "0Q001110zz1mmmmm010101nnnnnddddd") //INST(SRSHL_2, "SRSHL", "0Q001110zz1mmmmm010101nnnnnddddd")

12
src/frontend/A64/translate/impl/simd_three_same.cpp
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@ -20,6 +20,18 @@ bool TranslatorVisitor::CMGT_reg_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd)
return true; return true;
} }
bool TranslatorVisitor::CMGE_reg_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
if (size == 0b11 && !Q) return ReservedValue();
const size_t esize = 8 << size.ZeroExtend<size_t>();
const size_t datasize = Q ? 128 : 64;
const IR::U128 operand1 = V(datasize, Vn);
const IR::U128 operand2 = V(datasize, Vm);
const IR::U128 result = ir.VectorGreaterEqualSigned(esize, operand1, operand2);
V(datasize, Vd, result);
return true;
}
bool TranslatorVisitor::SMAX(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { bool TranslatorVisitor::SMAX(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
if (size == 0b11) { if (size == 0b11) {
return ReservedValue(); return ReservedValue();