A64: Implement SSUBW/SSUBW2
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3 changed files with 18 additions and 2 deletions
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@ -678,7 +678,7 @@ INST(NOT, "NOT", "0Q101
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//INST(SADDL, "SADDL, SADDL2", "0Q001110zz1mmmmm000000nnnnnddddd")
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INST(SADDW, "SADDW, SADDW2", "0Q001110zz1mmmmm000100nnnnnddddd")
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//INST(SSUBL, "SSUBL, SSUBL2", "0Q001110zz1mmmmm001000nnnnnddddd")
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//INST(SSUBW, "SSUBW, SSUBW2", "0Q001110zz1mmmmm001100nnnnnddddd")
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INST(SSUBW, "SSUBW, SSUBW2", "0Q001110zz1mmmmm001100nnnnnddddd")
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//INST(ADDHN, "ADDHN, ADDHN2", "0Q001110zz1mmmmm010000nnnnnddddd")
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//INST(SABAL, "SABAL, SABAL2", "0Q001110zz1mmmmm010100nnnnnddddd")
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//INST(SUBHN, "SUBHN, SUBHN2", "0Q001110zz1mmmmm011000nnnnnddddd")
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@ -805,7 +805,7 @@ struct TranslatorVisitor final {
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bool SADDL(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd);
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bool SADDW(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
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bool SSUBL(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd);
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bool SSUBW(bool Q, Imm<2> size, Reg Rm, Vec Vn, Vec Vd);
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bool SSUBW(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
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bool ADDHN(bool Q, Imm<2> size, Vec Vm, Vec Vn, Reg Rd);
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bool SABAL(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd);
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bool SUBHN(bool Q, Imm<2> size, Vec Vm, Vec Vn, Reg Rd);
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@ -24,6 +24,22 @@ bool TranslatorVisitor::SADDW(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
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return true;
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}
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bool TranslatorVisitor::SSUBW(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
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if (size == 0b11) {
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return ReservedValue();
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}
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const size_t esize = 8 << size.ZeroExtend();
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const size_t part = Q ? 1 : 0;
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const IR::U128 operand1 = V(128, Vn);
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const IR::U128 operand2 = ir.VectorSignExtend(esize, Vpart(64, Vm, part));
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const IR::U128 result = ir.VectorSub(esize * 2, operand1, operand2);
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V(128, Vd, result);
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return true;
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}
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bool TranslatorVisitor::UADDW(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
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if (size == 0b11) {
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return ReservedValue();
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