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ir/frontend: Add half-precision opcode for FPVectorMulAdd

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Lioncash 2019-04-13 01:42:35 -04:00 committed by MerryMage
parent 5f74d25bf7
commit ec6b3ae084
4 changed files with 37 additions and 27 deletions
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6
src/backend/x64/emit_x64_vector_floating_point.cpp
View file

@ -908,6 +908,7 @@ void EmitFPVectorMulAdd(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) {
} }
}; };
if constexpr (fsize != 16) {
if (code.DoesCpuSupport(Xbyak::util::Cpu::tFMA) && code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) { if (code.DoesCpuSupport(Xbyak::util::Cpu::tFMA) && code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
auto args = ctx.reg_alloc.GetArgumentInfo(inst); auto args = ctx.reg_alloc.GetArgumentInfo(inst);
@ -942,10 +943,15 @@ void EmitFPVectorMulAdd(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) {
ctx.reg_alloc.DefineValue(inst, result); ctx.reg_alloc.DefineValue(inst, result);
return; return;
} }
}
EmitFourOpFallback(code, ctx, inst, fallback_fn); EmitFourOpFallback(code, ctx, inst, fallback_fn);
} }
void EmitX64::EmitFPVectorMulAdd16(EmitContext& ctx, IR::Inst* inst) {
EmitFPVectorMulAdd<16>(code, ctx, inst);
}
void EmitX64::EmitFPVectorMulAdd32(EmitContext& ctx, IR::Inst* inst) { void EmitX64::EmitFPVectorMulAdd32(EmitContext& ctx, IR::Inst* inst) {
EmitFPVectorMulAdd<32>(code, ctx, inst); EmitFPVectorMulAdd<32>(code, ctx, inst);
} }

2
src/frontend/ir/ir_emitter.cpp
View file

@ -2173,6 +2173,8 @@ U128 IREmitter::FPVectorMul(size_t esize, const U128& a, const U128& b) {
U128 IREmitter::FPVectorMulAdd(size_t esize, const U128& a, const U128& b, const U128& c) { U128 IREmitter::FPVectorMulAdd(size_t esize, const U128& a, const U128& b, const U128& c) {
switch (esize) { switch (esize) {
case 16:
return Inst<U128>(Opcode::FPVectorMulAdd16, a, b, c);
case 32: case 32:
return Inst<U128>(Opcode::FPVectorMulAdd32, a, b, c); return Inst<U128>(Opcode::FPVectorMulAdd32, a, b, c);
case 64: case 64:

1
src/frontend/ir/microinstruction.cpp
View file

@ -327,6 +327,7 @@ bool Inst::ReadsFromAndWritesToFPSRCumulativeExceptionBits() const {
case Opcode::FPVectorGreaterEqual64: case Opcode::FPVectorGreaterEqual64:
case Opcode::FPVectorMul32: case Opcode::FPVectorMul32:
case Opcode::FPVectorMul64: case Opcode::FPVectorMul64:
case Opcode::FPVectorMulAdd16:
case Opcode::FPVectorMulAdd32: case Opcode::FPVectorMulAdd32:
case Opcode::FPVectorMulAdd64: case Opcode::FPVectorMulAdd64:
case Opcode::FPVectorPairedAddLower32: case Opcode::FPVectorPairedAddLower32:

1
src/frontend/ir/opcodes.inc
View file

@ -553,6 +553,7 @@ OPCODE(FPVectorMin32, U128, U128
OPCODE(FPVectorMin64, U128, U128, U128 ) OPCODE(FPVectorMin64, U128, U128, U128 )
OPCODE(FPVectorMul32, U128, U128, U128 ) OPCODE(FPVectorMul32, U128, U128, U128 )
OPCODE(FPVectorMul64, U128, U128, U128 ) OPCODE(FPVectorMul64, U128, U128, U128 )
OPCODE(FPVectorMulAdd16, U128, U128, U128, U128 )
OPCODE(FPVectorMulAdd32, U128, U128, U128, U128 ) OPCODE(FPVectorMulAdd32, U128, U128, U128, U128 )
OPCODE(FPVectorMulAdd64, U128, U128, U128, U128 ) OPCODE(FPVectorMulAdd64, U128, U128, U128, U128 )
OPCODE(FPVectorMulX32, U128, U128, U128 ) OPCODE(FPVectorMulX32, U128, U128, U128 )