A64: Implement CMLE (zero)'s vector variant
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2 changed files with 21 additions and 1 deletions
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@ -619,7 +619,7 @@ INST(REV32_asimd, "REV32 (vector)", "0Q101
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//INST(UADALP, "UADALP", "0Q101110zz100000011010nnnnnddddd")
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//INST(UADALP, "UADALP", "0Q101110zz100000011010nnnnnddddd")
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//INST(SQNEG_2, "SQNEG", "0Q101110zz100000011110nnnnnddddd")
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//INST(SQNEG_2, "SQNEG", "0Q101110zz100000011110nnnnnddddd")
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INST(CMGE_zero_2, "CMGE (zero)", "0Q101110zz100000100010nnnnnddddd")
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INST(CMGE_zero_2, "CMGE (zero)", "0Q101110zz100000100010nnnnnddddd")
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//INST(CMLE_2, "CMLE (zero)", "0Q101110zz100000100110nnnnnddddd")
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INST(CMLE_2, "CMLE (zero)", "0Q101110zz100000100110nnnnnddddd")
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INST(NEG_2, "NEG (vector)", "0Q101110zz100000101110nnnnnddddd")
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INST(NEG_2, "NEG (vector)", "0Q101110zz100000101110nnnnnddddd")
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//INST(SQXTUN_2, "SQXTUN, SQXTUN2", "0Q101110zz100001001010nnnnnddddd")
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//INST(SQXTUN_2, "SQXTUN, SQXTUN2", "0Q101110zz100001001010nnnnnddddd")
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//INST(SHLL, "SHLL, SHLL2", "0Q101110zz100001001110nnnnnddddd")
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//INST(SHLL, "SHLL, SHLL2", "0Q101110zz100001001110nnnnnddddd")
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@ -75,6 +75,26 @@ bool TranslatorVisitor::CMEQ_zero_2(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
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return true;
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return true;
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}
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}
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bool TranslatorVisitor::CMLE_2(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
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if (size == 0b11 && !Q) {
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return ReservedValue();
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}
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const size_t esize = 8 << size.ZeroExtend<size_t>();
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const size_t datasize = Q ? 128 : 64;
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const IR::U128 operand = V(datasize, Vn);
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const IR::U128 zero = ir.ZeroVector();
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IR::U128 result = ir.VectorLessEqualSigned(esize, operand, zero);
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if (datasize == 64) {
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result = ir.VectorZeroUpper(result);
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}
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V(datasize, Vd, result);
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return true;
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}
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bool TranslatorVisitor::ABS_2(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
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bool TranslatorVisitor::ABS_2(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
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if (!Q && size == 0b11) {
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if (!Q && size == 0b11) {
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return ReservedValue();
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return ReservedValue();
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