Support 64-bit immediates
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ff00b8c555
commit
f2fe376fc6
3 changed files with 14 additions and 7 deletions
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@ -16,14 +16,16 @@
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namespace Dynarmic {
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namespace BackendX64 {
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static u32 ImmediateToU32(const IR::Value& imm) {
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static u64 ImmediateToU64(const IR::Value& imm) {
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switch (imm.GetType()) {
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case IR::Type::U1:
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return u32(imm.GetU1());
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return u64(imm.GetU1());
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case IR::Type::U8:
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return u32(imm.GetU8());
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return u64(imm.GetU8());
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case IR::Type::U32:
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return u32(imm.GetU32());
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return u64(imm.GetU32());
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case IR::Type::U64:
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return u64(imm.GetU64());
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default:
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ASSERT_MSG(false, "This should never happen.");
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}
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@ -477,11 +479,11 @@ HostLoc RegAlloc::LoadImmediateIntoHostLocReg(IR::Value imm, HostLoc host_loc) {
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Xbyak::Reg64 reg = HostLocToReg64(host_loc);
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u32 imm_value = ImmediateToU32(imm);
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u64 imm_value = ImmediateToU64(imm);
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if (imm_value == 0)
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code->xor_(reg, reg);
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code->xor_(reg.cvt32(), reg.cvt32());
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else
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code->mov(reg.cvt32(), imm_value);
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code->mov(reg, imm_value);
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return host_loc;
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}
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@ -37,6 +37,10 @@ Value IREmitter::Imm32(u32 imm32) {
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return Value(imm32);
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}
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Value IREmitter::Imm64(u64 imm64) {
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return Value(imm64);
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}
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Value IREmitter::GetRegister(Arm::Reg reg) {
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if (reg == Arm::Reg::PC) {
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return Imm32(PC());
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@ -56,6 +56,7 @@ public:
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Value Imm1(bool value);
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Value Imm8(u8 value);
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Value Imm32(u32 value);
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Value Imm64(u64 value);
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Value GetRegister(Arm::Reg source_reg);
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Value GetExtendedRegister(Arm::ExtReg source_reg);
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