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translate_arm/extension: Invert conditionals where applicable

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Lioncash 2019-03-01 00:31:46 -05:00 committed by MerryMage
parent c2de6ecfd0
commit f4b19a7393
1 changed files with 142 additions and 95 deletions
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231
src/frontend/A32/translate/translate_arm/extension.cpp
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@ -13,170 +13,217 @@ static IR::U32 Rotate(A32::IREmitter& ir, Reg m, SignExtendRotation rotate) {
return ir.RotateRight(ir.GetRegister(m), ir.Imm8(rotate_by), ir.Imm1(0)).result;
}
// SXTAB<c> <Rd>, <Rn>, <Rm>{, <rotation>}
bool ArmTranslatorVisitor::arm_SXTAB(Cond cond, Reg n, Reg d, SignExtendRotation rotate, Reg m) {
if (d == Reg::PC || m == Reg::PC)
if (d == Reg::PC || m == Reg::PC) {
return UnpredictableInstruction();
// SXTAB <Rd>, <Rn>, <Rm>, <rotate>
if (ConditionPassed(cond)) {
auto rotated = Rotate(ir, m, rotate);
auto reg_n = ir.GetRegister(n);
auto result = ir.Add(reg_n, ir.SignExtendByteToWord(ir.LeastSignificantByte(rotated)));
ir.SetRegister(d, result);
}
if (!ConditionPassed(cond)) {
return true;
}
const auto rotated = Rotate(ir, m, rotate);
const auto reg_n = ir.GetRegister(n);
const auto result = ir.Add(reg_n, ir.SignExtendByteToWord(ir.LeastSignificantByte(rotated)));
ir.SetRegister(d, result);
return true;
}
// SXTAB16<c> <Rd>, <Rn>, <Rm>{, <rotation>}
bool ArmTranslatorVisitor::arm_SXTAB16(Cond cond, Reg n, Reg d, SignExtendRotation rotate, Reg m) {
if (d == Reg::PC || m == Reg::PC)
if (d == Reg::PC || m == Reg::PC) {
return UnpredictableInstruction();
// SXTAB16 <Rd>, <Rn>, <Rm>, <rotate>
if (ConditionPassed(cond)) {
auto rotated = Rotate(ir, m, rotate);
auto low_byte = ir.And(rotated, ir.Imm32(0x00FF00FF));
auto sign_bit = ir.And(rotated, ir.Imm32(0x00800080));
auto addend = ir.Or(low_byte, ir.Mul(sign_bit, ir.Imm32(0x1FE)));
auto result = ir.PackedAddU16(addend, ir.GetRegister(n)).result;
ir.SetRegister(d, result);
}
if (!ConditionPassed(cond)) {
return true;
}
const auto rotated = Rotate(ir, m, rotate);
const auto low_byte = ir.And(rotated, ir.Imm32(0x00FF00FF));
const auto sign_bit = ir.And(rotated, ir.Imm32(0x00800080));
const auto addend = ir.Or(low_byte, ir.Mul(sign_bit, ir.Imm32(0x1FE)));
const auto result = ir.PackedAddU16(addend, ir.GetRegister(n)).result;
ir.SetRegister(d, result);
return true;
}
// SXTAH<c> <Rd>, <Rn>, <Rm>{, <rotation>}
bool ArmTranslatorVisitor::arm_SXTAH(Cond cond, Reg n, Reg d, SignExtendRotation rotate, Reg m) {
if (d == Reg::PC || m == Reg::PC)
if (d == Reg::PC || m == Reg::PC) {
return UnpredictableInstruction();
// SXTAH <Rd>, <Rn>, <Rm>, <rotate>
if (ConditionPassed(cond)) {
auto rotated = Rotate(ir, m, rotate);
auto reg_n = ir.GetRegister(n);
auto result = ir.Add(reg_n, ir.SignExtendHalfToWord(ir.LeastSignificantHalf(rotated)));
ir.SetRegister(d, result);
}
if (!ConditionPassed(cond)) {
return true;
}
const auto rotated = Rotate(ir, m, rotate);
const auto reg_n = ir.GetRegister(n);
const auto result = ir.Add(reg_n, ir.SignExtendHalfToWord(ir.LeastSignificantHalf(rotated)));
ir.SetRegister(d, result);
return true;
}
// SXTB<c> <Rd>, <Rm>{, <rotation>}
bool ArmTranslatorVisitor::arm_SXTB(Cond cond, Reg d, SignExtendRotation rotate, Reg m) {
if (d == Reg::PC || m == Reg::PC)
if (d == Reg::PC || m == Reg::PC) {
return UnpredictableInstruction();
// SXTB <Rd>, <Rm>, <rotate>
if (ConditionPassed(cond)) {
auto rotated = Rotate(ir, m, rotate);
auto result = ir.SignExtendByteToWord(ir.LeastSignificantByte(rotated));
ir.SetRegister(d, result);
}
if (!ConditionPassed(cond)) {
return true;
}
const auto rotated = Rotate(ir, m, rotate);
const auto result = ir.SignExtendByteToWord(ir.LeastSignificantByte(rotated));
ir.SetRegister(d, result);
return true;
}
// SXTB16<c> <Rd>, <Rm>{, <rotation>}
bool ArmTranslatorVisitor::arm_SXTB16(Cond cond, Reg d, SignExtendRotation rotate, Reg m) {
if (d == Reg::PC || m == Reg::PC)
if (d == Reg::PC || m == Reg::PC) {
return UnpredictableInstruction();
// SXTB16 <Rd>, <Rm>, <rotate>
if (ConditionPassed(cond)) {
auto rotated = Rotate(ir, m, rotate);
auto low_byte = ir.And(rotated, ir.Imm32(0x00FF00FF));
auto sign_bit = ir.And(rotated, ir.Imm32(0x00800080));
auto result = ir.Or(low_byte, ir.Mul(sign_bit, ir.Imm32(0x1FE)));
ir.SetRegister(d, result);
}
if (!ConditionPassed(cond)) {
return true;
}
const auto rotated = Rotate(ir, m, rotate);
const auto low_byte = ir.And(rotated, ir.Imm32(0x00FF00FF));
const auto sign_bit = ir.And(rotated, ir.Imm32(0x00800080));
const auto result = ir.Or(low_byte, ir.Mul(sign_bit, ir.Imm32(0x1FE)));
ir.SetRegister(d, result);
return true;
}
// SXTH<c> <Rd>, <Rm>{, <rotation>}
bool ArmTranslatorVisitor::arm_SXTH(Cond cond, Reg d, SignExtendRotation rotate, Reg m) {
if (d == Reg::PC || m == Reg::PC)
if (d == Reg::PC || m == Reg::PC) {
return UnpredictableInstruction();
// SXTH <Rd>, <Rm>, <rotate>
if (ConditionPassed(cond)) {
auto rotated = Rotate(ir, m, rotate);
auto result = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(rotated));
ir.SetRegister(d, result);
}
if (!ConditionPassed(cond)) {
return true;
}
const auto rotated = Rotate(ir, m, rotate);
const auto result = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(rotated));
ir.SetRegister(d, result);
return true;
}
// UXTAB<c> <Rd>, <Rn>, <Rm>{, <rotation>}
bool ArmTranslatorVisitor::arm_UXTAB(Cond cond, Reg n, Reg d, SignExtendRotation rotate, Reg m) {
if (d == Reg::PC || m == Reg::PC)
if (d == Reg::PC || m == Reg::PC) {
return UnpredictableInstruction();
// UXTAB <Rd>, <Rn>, <Rm>, <rotate>
if (ConditionPassed(cond)) {
auto rotated = Rotate(ir, m, rotate);
auto reg_n = ir.GetRegister(n);
auto result = ir.Add(reg_n, ir.ZeroExtendByteToWord(ir.LeastSignificantByte(rotated)));
ir.SetRegister(d, result);
}
if (!ConditionPassed(cond)) {
return true;
}
const auto rotated = Rotate(ir, m, rotate);
const auto reg_n = ir.GetRegister(n);
const auto result = ir.Add(reg_n, ir.ZeroExtendByteToWord(ir.LeastSignificantByte(rotated)));
ir.SetRegister(d, result);
return true;
}
// UXTAB16<c> <Rd>, <Rn>, <Rm>{, <rotation>}
bool ArmTranslatorVisitor::arm_UXTAB16(Cond cond, Reg n, Reg d, SignExtendRotation rotate, Reg m) {
if (d == Reg::PC || m == Reg::PC || n == Reg::PC)
if (d == Reg::PC || m == Reg::PC || n == Reg::PC) {
return UnpredictableInstruction();
}
// UXTAB16 <Rd>, <Rn>, <Rm>, <rotate>
if (ConditionPassed(cond)) {
auto rotated = Rotate(ir, m, rotate);
if (!ConditionPassed(cond)) {
return true;
}
const auto rotated = Rotate(ir, m, rotate);
auto result = ir.And(rotated, ir.Imm32(0x00FF00FF));
auto reg_n = ir.GetRegister(n);
const auto reg_n = ir.GetRegister(n);
result = ir.PackedAddU16(reg_n, result).result;
ir.SetRegister(d, result);
}
return true;
}
// UXTAH<c> <Rd>, <Rn>, <Rm>{, <rotation>}
bool ArmTranslatorVisitor::arm_UXTAH(Cond cond, Reg n, Reg d, SignExtendRotation rotate, Reg m) {
if (d == Reg::PC || m == Reg::PC)
if (d == Reg::PC || m == Reg::PC) {
return UnpredictableInstruction();
// UXTAH <Rd>, <Rn>, <Rm>, <rotate>
if (ConditionPassed(cond)) {
auto rotated = Rotate(ir, m, rotate);
auto reg_n = ir.GetRegister(n);
auto result = ir.Add(reg_n, ir.ZeroExtendHalfToWord(ir.LeastSignificantHalf(rotated)));
ir.SetRegister(d, result);
}
if (!ConditionPassed(cond)) {
return true;
}
const auto rotated = Rotate(ir, m, rotate);
const auto reg_n = ir.GetRegister(n);
const auto result = ir.Add(reg_n, ir.ZeroExtendHalfToWord(ir.LeastSignificantHalf(rotated)));
ir.SetRegister(d, result);
return true;
}
// UXTB<c> <Rd>, <Rm>{, <rotation>}
bool ArmTranslatorVisitor::arm_UXTB(Cond cond, Reg d, SignExtendRotation rotate, Reg m) {
if (d == Reg::PC || m == Reg::PC)
if (d == Reg::PC || m == Reg::PC) {
return UnpredictableInstruction();
// UXTB <Rd>, <Rm>, <rotate>
if (ConditionPassed(cond)) {
auto rotated = Rotate(ir, m, rotate);
auto result = ir.ZeroExtendByteToWord(ir.LeastSignificantByte(rotated));
ir.SetRegister(d, result);
}
if (!ConditionPassed(cond)) {
return true;
}
const auto rotated = Rotate(ir, m, rotate);
const auto result = ir.ZeroExtendByteToWord(ir.LeastSignificantByte(rotated));
ir.SetRegister(d, result);
return true;
}
// UXTB16<c> <Rd>, <Rm>{, <rotation>}
bool ArmTranslatorVisitor::arm_UXTB16(Cond cond, Reg d, SignExtendRotation rotate, Reg m) {
if (d == Reg::PC || m == Reg::PC)
if (d == Reg::PC || m == Reg::PC) {
return UnpredictableInstruction();
// UXTB16 <Rd>, <Rm>, <rotate>
if (ConditionPassed(cond)) {
auto rotated = Rotate(ir, m, rotate);
auto result = ir.And(rotated, ir.Imm32(0x00FF00FF));
ir.SetRegister(d, result);
}
if (!ConditionPassed(cond)) {
return true;
}
const auto rotated = Rotate(ir, m, rotate);
const auto result = ir.And(rotated, ir.Imm32(0x00FF00FF));
ir.SetRegister(d, result);
return true;
}
// UXTH<c> <Rd>, <Rm>{, <rotation>}
bool ArmTranslatorVisitor::arm_UXTH(Cond cond, Reg d, SignExtendRotation rotate, Reg m) {
if (d == Reg::PC || m == Reg::PC)
if (d == Reg::PC || m == Reg::PC) {
return UnpredictableInstruction();
// UXTH <Rd>, <Rm>, <rotate>
if (ConditionPassed(cond)) {
auto rotated = Rotate(ir, m, rotate);
auto result = ir.ZeroExtendHalfToWord(ir.LeastSignificantHalf(rotated));
ir.SetRegister(d, result);
}
if (!ConditionPassed(cond)) {
return true;
}
const auto rotated = Rotate(ir, m, rotate);
const auto result = ir.ZeroExtendHalfToWord(ir.LeastSignificantHalf(rotated));
ir.SetRegister(d, result);
return true;
}