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A32: Implement ASIMD VMVN (register)

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Fairly straightforward
This commit is contained in:
Lioncash 2020-06-18 21:58:17 -04:00 committed by merry
parent b759773b3b
commit fbdae61c13
3 changed files with 21 additions and 1 deletions
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2
src/frontend/A32/decoder/asimd.inc
View file

@ -81,7 +81,7 @@ INST(asimd_VREV, "VREV{16,32,64}", "111100111D11zz00dddd000
INST(asimd_VCLS, "VCLS", "111100111D11zz00dddd01000QM0mmmm") // ASIMD INST(asimd_VCLS, "VCLS", "111100111D11zz00dddd01000QM0mmmm") // ASIMD
INST(asimd_VCLZ, "VCLZ", "111100111D11zz00dddd01001QM0mmmm") // ASIMD INST(asimd_VCLZ, "VCLZ", "111100111D11zz00dddd01001QM0mmmm") // ASIMD
INST(asimd_VCNT, "VCNT", "111100111D11zz00dddd01010QM0mmmm") // ASIMD INST(asimd_VCNT, "VCNT", "111100111D11zz00dddd01010QM0mmmm") // ASIMD
//INST(asimd_VMVN_reg, "VMVN_reg", "111100111-11--00----01011x-0----") // ASIMD INST(asimd_VMVN_reg, "VMVN_reg", "111100111D11zz00dddd01011QM0mmmm") // ASIMD
//INST(asimd_VPADAL, "VPADAL", "111100111-11--00----0110xx-0----") // ASIMD //INST(asimd_VPADAL, "VPADAL", "111100111-11--00----0110xx-0----") // ASIMD
INST(asimd_VQABS, "VQABS", "111100111D11zz00dddd01110QM0mmmm") // ASIMD INST(asimd_VQABS, "VQABS", "111100111D11zz00dddd01110QM0mmmm") // ASIMD
INST(asimd_VQNEG, "VQNEG", "111100111D11zz00dddd01111QM0mmmm") // ASIMD INST(asimd_VQNEG, "VQNEG", "111100111D11zz00dddd01111QM0mmmm") // ASIMD

19
src/frontend/A32/translate/impl/asimd_two_regs_misc.cpp
View file

@ -133,6 +133,25 @@ bool ArmTranslatorVisitor::asimd_VCNT(bool D, size_t sz, size_t Vd, bool Q, bool
return true; return true;
} }
bool ArmTranslatorVisitor::asimd_VMVN_reg(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm) {
if (sz != 0b00) {
return UndefinedInstruction();
}
if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) {
return UndefinedInstruction();
}
const auto d = ToVector(Q, Vd, D);
const auto m = ToVector(Q, Vm, M);
const auto reg_m = ir.GetVector(m);
const auto result = ir.VectorNot(reg_m);
ir.SetVector(d, result);
return true;
}
bool ArmTranslatorVisitor::asimd_VQABS(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm) { bool ArmTranslatorVisitor::asimd_VQABS(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm) {
if (sz == 0b11) { if (sz == 0b11) {
return UndefinedInstruction(); return UndefinedInstruction();

1
src/frontend/A32/translate/impl/translate_arm.h
View file

@ -466,6 +466,7 @@ struct ArmTranslatorVisitor final {
bool asimd_VCLS(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm); bool asimd_VCLS(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm);
bool asimd_VCLZ(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm); bool asimd_VCLZ(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm);
bool asimd_VCNT(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm); bool asimd_VCNT(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm);
bool asimd_VMVN_reg(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm);
bool asimd_VQABS(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm); bool asimd_VQABS(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm);
bool asimd_VQNEG(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm); bool asimd_VQNEG(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm);
bool asimd_VABS(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm); bool asimd_VABS(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm);