Merry
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2c75ca746b
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backend/arm64/stack_layout: Remove unused variable
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2022-10-18 15:04:30 +01:00 |
|
Merry
|
72357aba04
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emit_arm64_vector: Implement VectorBroadcast
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2022-10-18 15:04:30 +01:00 |
|
Merry
|
3c3f30c0ac
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emit_arm64_vector: Implement Vector{Get,Set}Element
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2022-10-18 15:04:30 +01:00 |
|
Merry
|
ee6433889e
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emit_arm64_floating_point: Implement a majority of floating point instructions
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2022-10-18 15:04:30 +01:00 |
|
Merry
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2cc5b09bdf
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emit_arm64_data_processing: Implement ConditionalSelect
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2022-10-18 15:04:30 +01:00 |
|
Merry
|
a4a665148c
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emit_arm64_a32: Get/Set ext_reg state
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2022-10-18 15:04:30 +01:00 |
|
Merry
|
0288540155
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backend/arm64/reg_alloc: Implement ReadWrite mode
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2022-10-18 15:04:30 +01:00 |
|
Merry
|
208b19b89a
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backend/arm64: FPCR/FPSR handling
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2022-10-18 15:04:30 +01:00 |
|
Merry
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60a119da6a
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backend: Implement FpsrManager
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2022-10-18 15:04:30 +01:00 |
|
Merry
|
72026c91b5
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oaknut: fpsimd MOV and UMOV corrections
|
2022-10-18 15:04:30 +01:00 |
|
Merry
|
3b98af5810
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test_generator: Generate Arm instructions
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2022-10-18 15:04:30 +01:00 |
|
Merry
|
2ac12562ab
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emit_arm64: Handle cond prologue
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2022-10-18 15:04:30 +01:00 |
|
Merry
|
aa6b31f2b8
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emit_arm64: Handle 64-bit values in GetNZFromOp
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2022-10-18 15:04:30 +01:00 |
|
Merry
|
5086432f19
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a32_emit_x64: EmitA32SetCpsr: Correct cpsr_jaifm mask
|
2022-10-18 15:04:30 +01:00 |
|
Merry
|
23c23fbca3
|
arm64/reg_alloc: Bugfix in ValueInfo
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2022-10-18 15:04:30 +01:00 |
|
Merry
|
6dfd94f3fb
|
arm64/reg_alloc: Ban materialization of U1 constants
|
2022-10-18 15:04:30 +01:00 |
|
Merry
|
73b48448cb
|
emit_arm64_data_processing: Handle immediate carry in for shift instructions
|
2022-10-18 15:04:30 +01:00 |
|
Merry
|
db5db43fd4
|
emit_arm64_a32: A32SetCpsrNZC: Handle immediate
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2022-10-18 15:04:30 +01:00 |
|
Merry
|
65a7d9be8d
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emit_arm64_a32: A32SetCheckBit: Handle immediate
|
2022-10-18 15:04:30 +01:00 |
|
Merry
|
49589168c9
|
oaknut: MOV: Fix MOVN case
|
2022-10-18 15:04:30 +01:00 |
|
Merry
|
8649345886
|
emit_arm64_cryptography: Implement CRC
|
2022-10-18 15:04:30 +01:00 |
|
Merry
|
f84e489969
|
test_generator: Expand testing to thumb32
|
2022-10-18 15:04:30 +01:00 |
|
Merry
|
6d6cbe2e66
|
emit_arm64_saturation: Fix UnsignedSaturation for < 0
|
2022-10-18 15:04:30 +01:00 |
|
Merry
|
b059384bc0
|
emit_arm64_saturation: Implement SignedSaturatedSubWithFlag32
|
2022-10-18 15:04:30 +01:00 |
|
Merry
|
090e79add2
|
emit_arm64_data_processing: Implement CountLeadingZeros
|
2022-10-18 15:04:30 +01:00 |
|
Merry
|
e921c397ac
|
emit_arm64_data_processing: Fix BitImms for exceptional immediates
|
2022-10-18 15:04:30 +01:00 |
|
Merry
|
f642f49b93
|
emit_arm64_data_processing: Implement RotateRightExtended
|
2022-10-18 15:04:30 +01:00 |
|
Merry
|
22d87bcbe5
|
emit_arm64_a32: Implement A32SetGEFlagsCompressed
|
2022-10-18 15:04:30 +01:00 |
|
Merry
|
735f5b787a
|
emit_arm64_a32: Fix A32SetCpsrNZC for immediate carry
|
2022-10-18 15:04:30 +01:00 |
|
Merry
|
33b3376fb1
|
emit_arm64_a32: Implement A32SetCpsrNZCVRaw, A32SetCpsrNZCVQ
|
2022-10-18 15:04:30 +01:00 |
|
Merry
|
11b665c027
|
emit_arm64_a32: Implement A32SetCpsr (temporary implementation)
|
2022-10-18 15:04:30 +01:00 |
|
Merry
|
950400fb6b
|
arm64/a32_jitstate: Adjust structure
|
2022-10-18 15:04:30 +01:00 |
|
Merry
|
726e116e28
|
emit_arm64_saturation: Implement SignedSaturatedAddWithFlag32
|
2022-10-18 15:04:30 +01:00 |
|
Merry
|
babfb7d7b8
|
IR/saturation: Revamp saturated add/sub IR instructions
|
2022-10-18 15:04:30 +01:00 |
|
Merry
|
2d0bf7ca9b
|
emit_arm64_data_processing: Implement overflow output for Add
|
2022-10-18 15:04:30 +01:00 |
|
Merry
|
adb18fd0a7
|
emit_arm64_data_processing: Implement LogicalShift{Left,Right}64
|
2022-10-18 15:04:30 +01:00 |
|
Merry
|
0692f1d40e
|
emit_arm64_data_processing: EmitAddSub: Handle zero immediate w/ flag output
|
2022-10-18 15:04:30 +01:00 |
|
Merry
|
cd537dc711
|
IR: Rename PackedAbsDiffSumS8 to PackedAbsDiffSumU8
|
2022-10-18 15:04:30 +01:00 |
|
Merry
|
ee2bc92993
|
emit_arm64_saturation: Implement SignedSaturation
|
2022-10-18 15:04:30 +01:00 |
|
Merry
|
e73c390927
|
emit_arm64_packed: Fix signed packed add sub
|
2022-10-18 15:04:30 +01:00 |
|
Merry
|
c8b3be5512
|
emit_arm64_data_processing: Implement Div
|
2022-10-18 15:04:30 +01:00 |
|
Merry
|
a320a333e1
|
emit_arm64_packed: Implement PackedAbsDiffSumS8
|
2022-10-18 15:04:30 +01:00 |
|
Merry
|
0ebbc4a9c5
|
emit_arm64_packed: Implement PackedSelect
|
2022-10-18 15:04:30 +01:00 |
|
Merry
|
ac7908164a
|
emit_arm64_packed: Implement packed halving operations
|
2022-10-18 15:04:30 +01:00 |
|
Merry
|
d1909c5efb
|
emit_arm64_packed: Implement halving add sub exchange
|
2022-10-18 15:04:30 +01:00 |
|
Merry
|
ff34f4c6ae
|
emit_arm64_data_processing: Fix flag reading in AddSub
Also improve codegen for ZR case.
|
2022-10-18 15:04:30 +01:00 |
|
Merry
|
aaa0773695
|
emit_arm64_data_processing: Add carry output to MostSignificantWord
|
2022-10-18 15:04:30 +01:00 |
|
Merry
|
5c54c7d968
|
emit_arm64_packed: Implement packed add sub exchange
|
2022-10-18 15:04:30 +01:00 |
|
Merry
|
0bd7601844
|
emit_arm64_packed: Implement PackedSubU16
|
2022-10-18 15:04:30 +01:00 |
|
Merry
|
1810bd6547
|
emit_arm64_packed: Implement PackedSubU16
|
2022-10-18 15:04:30 +01:00 |
|