Commit graph

3269 commits

Author SHA1 Message Date
Lioncash
64e51a6d4d A32/disassembler_arm: Mark utility functions as static where applicable
These don't depend on class state and can be marked static to make that
explicit.
2020-04-22 21:02:46 +01:00
Lioncash
8103652a91 frontend: Move imm.h to the top-level directory of the frontends
Preparation to utilize the immediate type within the A32 backend as
well, which will allow eliminating numerous type aliases like Imm4,
Imm5, etc.
2020-04-22 21:02:46 +01:00
Lioncash
511613c736 frontend/A32/types: Use helper function in operator+ overload
Allows deduplicating an assert and a cast.
2020-04-22 21:02:46 +01:00
Mat M
c778816424 Merge pull request #487 from lioncash/fuzz2
a32/fuzz_arm: Use same fuzzing mechanism as AArch64
2020-04-22 21:02:46 +01:00
Lioncash
796bb8a7f7 frontend/A64/types: Make RegNumber() and VecNumber() constexpr
Given they simply perform casting, they can be safely made constexpr.
2020-04-22 21:02:46 +01:00
Merry
08c0cc84a8 Merge pull request #486 from lioncash/barrier
A32: Implement barrier instructions introduced in ARMv7
2020-04-22 21:02:46 +01:00
Lioncash
0b15fc9755 a32/fuzz_arm: Use same fuzzing mechanism as AArch64
Introduces the same fuzzing mechanism used by the AArch64 code for
fuzzing instruction implementations, getting rid of the need to
manually specify the instruction generator sequences--replacing it with
an instruction blacklist instead.

Much of this change originates from a previous patch made by Mary. This
just makes it interact nicely with the alterations made to get Unicorn
to cooperate properly.
2020-04-22 21:02:46 +01:00
Lioncash
0c43228ad5 frontend/A64/types: Use helper functions in operator+ overloads
Allows us to get rid of another explicit cast.
2020-04-22 21:02:46 +01:00
Mat M
07218df353 Merge pull request #485 from lioncash/a32
A32: Handle all ARM-mode arithmetic and data processing instructions added in ARMv6T2 and ARMv7
2020-04-22 21:02:46 +01:00
Lioncash
8316d231e9 A32: Implement barrier instructions introduced in ARMv7
Provides basic implementations of the barrier instruction introduced
within ARMv7. Currently these simply mirror the behavior of the AArch64
equivalents.
2020-04-22 21:02:46 +01:00
Lioncash
a1cace21a9 frontend/ir/ir_emitter: Apply const to locals where applicable
Makes const usage consistent with all other functions in the source
file.
2020-04-22 21:02:46 +01:00
Lioncash
d4a531c21f travis: Re-enable A32 tests 2020-04-22 21:02:46 +01:00
Lioncash
7fc3bd689d A32: Implement ARM-mode MLS 2020-04-22 21:02:46 +01:00
Lioncash
0a35836998 frontend/ir/ir_emitter: Use switch constructs in floating point opcodes where applicable
This'll reduce the amount of noise necessary in changes implementing
half-precision instructions, as the type can just be prepended to the
switch cases, instead of rewriting the whole if/else branch.
2020-04-22 21:02:46 +01:00
Lioncash
2acfee66ed a32_unicorn: Silence PC value assertions
Ensure the PC is properly masked off after a run.
2020-04-22 21:02:46 +01:00
Lioncash
8b338b7def A32: Implement ARM-mode MOVT 2020-04-22 21:02:46 +01:00
Lioncash
2641d410a4 travis: Amend build parameters
Currently just run the 64-bit tests.
2020-04-22 21:02:46 +01:00
Lioncash
877fa0f8c3 A32: Implement ARM-mode SBFX 2020-04-22 21:02:46 +01:00
Lioncash
57be160524 fuzz_arm: Tidy up existing tests
Now that we utilize C++17, we can use std::array's deduction guides to
avoid the need to explicitly specify the template arguments.

While we're at it, also use const where applicable.
2020-04-22 21:02:46 +01:00
Lioncash
47218ee65d A32: Implement ARM-mode UBFX 2020-04-22 21:02:46 +01:00
Lioncash
a77ca35ec3 Merge branch 'fuzz' 2020-04-22 21:02:46 +01:00
Lioncash
2970b34e3c A32: Implement ARM-mode BFI 2020-04-22 21:02:46 +01:00
Lioncash
c0ae23bbb7 A32/translate_thumb: Clean up formatting
Performs a similar tidying up of the Thumb translator, like what was
done with the regular ARM translator to make it consistent with the rest
of the codebase.

The A32 backend (both Thumb and ARM), will likely see more changes to it
in the near future, so this just acts as a "dusting off".
2020-04-22 21:02:46 +01:00
Lioncash
fab3a59e05 A32: Implement ARM-mode BFC 2020-04-22 21:02:46 +01:00
Merry
837c23a8ec Merge pull request #483 from lioncash/invert
frontend/ir/cond: Remove unused invert() function
2020-04-22 21:02:46 +01:00
Lioncash
7305d13221 A32: Implement ARM-mode RBIT 2020-04-22 21:02:46 +01:00
Lioncash
d12e375481 common/fp/op/FPConvert: Remove unnecessary casts in FPConvert()
These were made unnecessary in 2c2fdb435cf8e358a0c5b907ce8131e434df3f22,
but were missed during the initial removal.
2020-04-22 21:02:46 +01:00
Lioncash
b2f7a0e7ba A32: Implement ARM-mode SDIV/UDIV
Now that we have Unicorn in place, we can freely implement instructions
introduced in newer versions of the ARM architecture.
2020-04-22 21:02:46 +01:00
Lioncash
4f2b60c8e7 dynarmic_tests: Remove skyeye interpreter
This is quite a messy interpreter and would require a large amount of
work to bring it up to speed to begin implementing newer portions of the
AArch32 instruction set into Dynarmic.

Given we already have fuzzing with Unicorn set up for
AArch64/AArch32, we can get rid of this and unify our testing
infrastructure.

This will also make building the tests much faster, given a whole
interpreter doesn't need to be built anymore as part of the project.
2020-04-22 21:02:45 +01:00
Merry
09ee64ea98 Merge pull request #482 from lioncash/fixedfp
A64: Handle half-precision variants of FP->Fixed instructions
2020-04-22 21:02:45 +01:00
Lioncash
d29582a0e1 A32: Fuzz instructions using unicorn
While skyeye was OK previously, now that we have an AArch64 backend,
this also means that we eventually have to support the AArch32
counterpart to it. Unfortunately, SkyEye is only compatible up to
ARMv6K, so we woud need to do a lot of work to bring the interpreter up
to speed with things to even begin testing new instruction
implementations.

For the AArch64 side of things, we already use Unicorn, so we can toss
out SkyEye in favor of it instead.
2020-04-22 21:02:45 +01:00
MerryMage
1e1e9c17c7 emit_x64_data_processing: Remove INVALID_REG
INVALID_REG.cvt8() now throws
2020-04-22 21:02:45 +01:00
MerryMage
76768f9083 Squashed 'externals/xbyak/' changes from 4a6fac8ad..73ac58660
73ac58660 fix Reg::changeBit

git-subtree-dir: externals/xbyak
git-subtree-split: 73ac5866099b19bd8063f06434e19b9d7bbc9b8d
2020-04-22 21:02:25 +01:00
MerryMage
31a17c91c1 externals: Update xbyak to 73ac586
Merge commit '76768f908381248e9ae32f4a4c82d3765ef2afa0' into HEAD
2020-04-22 21:02:25 +01:00
Lioncash
06ec6ab0da frontend/ir/cond: Remove unused invert() function
This is no longer used by anything in the codebase, so it can be
removed.
2020-04-22 21:01:46 +01:00
Merry
d71f51b0da Merge pull request #481 from lioncash/alloc
ir/basic_block: Forward declare headers where applicable
2020-04-22 21:01:46 +01:00
Lioncash
64e3d233f4 A64: Handle half-precision variants of FP->Fixed-point instructions 2020-04-22 21:01:45 +01:00
Merry
2d3aa9b8fb Merge pull request #480 from lioncash/info
common/fp/info: Make half-precision info struct functions return correctly sized types
2020-04-22 21:01:45 +01:00
Lioncash
4fc531f71b ir/basic_block: Forward declare headers where applicable
Now that the constructor and destructors have been placed within the cpp
file, we can forward declare the memory pool data structures. Now, a
change to the memory pool code won't ripple across the entirety of the
IR emitter.
2020-04-22 21:01:45 +01:00
Lioncash
427b7afd66 frontend/ir/microinstruction: Add missing fixed-point opcodes to ReadsFromAndWritesToFPSRCumulativeExceptionBits() 2020-04-22 21:01:45 +01:00
Merry
699ad98b2a Merge pull request #479 from lioncash/rsqrts
A64: Handle half-precision variants of FRSQRTS
2020-04-22 21:01:45 +01:00
Lioncash
c9777ef997 common/fp/info: Make half-precision info struct functions return correctly sized types
While initially done to potentially prevent creating bugs due to C++
having a silly type-promotion mechanism involving types < sizeof(int)
and unsignedness, given that the bulk of these functions' usages
are on exit paths, these can return the correct type to avoid the need
to cast at every usage point.
2020-04-22 21:01:45 +01:00
Lioncash
9309d95b17 ir/block: Default ctor and dtor in the cpp file
Prevents potentially inlining allocation code everywhere. While we're at
it, also explicitly delete/default the copy/move constructor/assignment
operators to be explicit about them.
2020-04-22 21:01:45 +01:00
Lioncash
604f39f00a frontend/ir_emitter: Add half-precision->fixed-point opcodes 2020-04-22 21:01:45 +01:00
Lioncash
471eb77bc9 A64: Implement FRSQRTS' half-precision vector variant 2020-04-22 21:01:45 +01:00
Lioncash
4ecfbc14de common/fp/op/FPToFixed: Add half-precision specialization of FPToFixed 2020-04-22 21:01:45 +01:00
Lioncash
f9b2862217 A64: Implement FRSQRTS' half-precision scalar variant
With the necessary machinery in place, we can now handle the
half-precision variant.
2020-04-22 21:01:45 +01:00
Lioncash
96356fac93 frontend/ir_emitter: Add half-precision opcode variant of FPVectorRSqrtStepFused 2020-04-22 21:01:45 +01:00
Merry
45864133f5 Merge pull request #478 from lioncash/stepfused
A64: Handle half-precision variants of FRECPE and FRECPS
2020-04-22 21:01:44 +01:00
Lioncash
824c551ba2 frontend/ir_emitter: Add half-precision opcode variant of FPRSqrtStepFused 2020-04-22 21:01:44 +01:00