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Author SHA1 Message Date
Lioncash
2d59d10ac8 A64: Implement SQSHLU's vector variant 
The vector shift by immediate category is now fully implemented.
 2020-04-22 21:01:44 +01:00
Lioncash
a4cadf1cd9 frontend/ir_emitter: Add opcodes for signed saturated left shifts with unsigned saturation 2020-04-22 21:01:44 +01:00
Merry
b91c6c8bae Merge pull request #471 from lioncash/sqrdmulh 
A64: Implement SQRDMULH's scalar vector variant
 2020-04-22 21:01:44 +01:00
Merry
b5e25959d9 Merge pull request #470 from lioncash/assert 
general: Replace unreachable-imitating assertions with UNREACHABLE()
 2020-04-22 21:01:44 +01:00
Lioncash
3b46b4a37d A64: Implement SQRDMULH's scalar vector variant 
Implements the scalar variant in terms of the vector variant for the
time being.
 2020-04-22 21:01:43 +01:00
Lioncash
fe95575b95 general: Replace unreachable-imitating assertions with UNREACHABLE() 
We can just use the self-documenting assertion for indicating
unreachable paths, instead of manually passing false and providing a
message.
 2020-04-22 21:01:43 +01:00
Lioncash
64de80839e A64/impl: Reorganize peculiar void use in V_scalar 
To a reader this might look particularly strange, given the function
itself has a void return value, but this is actually valid, given the
function in the return statement also has a void return value.

This instead alters it to be a little easier to parse and potentially be
a little less confusing at a glance.
 2020-04-22 21:01:43 +01:00
Merry
9a4e3b24e4 Merge pull request #467 from lioncash/reserved 
A64: Handle reserved instruction cases more specifically where applicable
 2020-04-22 21:01:43 +01:00
Lioncash
8309d49588 A64: Handle reserved instruction cases more specifically where applicable 
These are cases that are defined as reserved within the ARMv8 reference
manual, so we can handle them as such instead of as unallocated
encodings.

While this doesn't actually change emulated behavior, it does at least
allow the JIT to generate the more appropriate exception.
 2020-04-22 21:00:47 +01:00
Lioncash
6c2c68bce6 A64: Implement FCMLA's indexed element variant 
With this, all of the instructions introduced with ARMv8.3-CompNum have
an implementation.
 2020-04-22 21:00:47 +01:00
Lioncash
7bc7042104 simd_scalar_shift_by_immediate: Change UnallocatedEncoding() path in SaturatingShiftLeft to ReservedValue() 
Strictly speaking, immh being zero is defined as reserved in the ARMv8
reference manual. This was just an error on my part when introducing the
SQSHL immediate scalar variant.
 2020-04-22 21:00:47 +01:00
Lioncash
b1b4487e4d A64: Implement UQSHL (immediate)'s scalar variant 
Like SQSHL's immediate scalar variant, we can also implement UQSHL's
immediate scalar variant in terms of the vector variant for the time
being.
 2020-04-22 21:00:47 +01:00
Lioncash
e1b4ff1068 simd_scalar_shift_by_immediate: Migrate SQSHL implementation to file-scope function 
This will allow it to be reused for the implementation of UQSHL.
 2020-04-22 21:00:47 +01:00
Lioncash
3649dc6d9a A64: Implement scalar variant of SQSHL (immediate) 
This can be handled in terms of the vector variant for the time being.
 2020-04-22 21:00:47 +01:00
Merry
01bb1cdd88 Merge pull request #458 from lioncash/float-op 
A64: Handle half-precision floating point in FABS, FNEG, and scalar FMOV
 2020-04-22 20:58:12 +01:00
Lioncash
28a8b4d210 A64: Handle half-precision floating point in scalar FMOV 
This is simply performing a scalar value transfer between registers
without conversions, so this is trivial to handle as-is.
 2020-04-22 20:58:12 +01:00
Lioncash
d7ac5a664f A64: Handle half-precision floating point in FCVTL 
Like FCVTN, now that we have half-precision floating point conversion
functions available, we can go ahead and use those to eliminate the
interpreter fallback.
 2020-04-22 20:58:12 +01:00
Lioncash
fe84ecb780 A64: Handle half-precision floating point in scalar FABS 
Now that we have the half-precision variant of the opcode added, we can
simply handle the instruction instead of treating it as undefined.
 2020-04-22 20:58:12 +01:00
Lioncash
fac9224d5e A64: Handle half-precision floating point in FCVTN 
Now that we have IR instructions for performing conversions with
half-precision floating point, we can also handle half-precision values
within FCVTN.
 2020-04-22 20:58:12 +01:00
Lioncash
8309ec7a9f frontend/ir_emitter: Add half-precision variant of FPAbs 2020-04-22 20:58:12 +01:00
Lioncash
16de99d3e3 A64: Enable FCVT floating-point conversions for half-precision 
With this, we no longer have to fall back to the interpreter in any of
the FCVT floating-point conversion instructions.
 2020-04-22 20:58:12 +01:00
Lioncash
10abc77fad A64: Handle half-precision floating point in scalar FNEG 
With the half-precision variant of the FPNeg opcode added, we can
utilize it here to emulate the half-precision variant of FNEG.
 2020-04-22 20:58:12 +01:00
Lioncash
e4c259d69f frontend/ir_emitter: Add half->{single, double} and {double, single}->half conversion opcodes 2020-04-22 20:58:12 +01:00
Lioncash
c97efcb978 frontend/ir_emitter: Add half-precision variant of FPNeg 2020-04-22 20:58:12 +01:00
Merry
f01afc5ae6 Merge pull request #456 from lioncash/mov 
A64: Enable FMOV (general) for half-precision floating point
 2020-04-22 20:58:12 +01:00
Merry
c1ce94872d Merge pull request #455 from lioncash/sqrdmulh-scalar 
A64: Implement SQRDMULH and SQDMULL's scalar indexed variants
 2020-04-22 20:58:11 +01:00
Lioncash
25a7256ee1 A64: Enable FMOV (general) for half-precision floating point 
This just transfers values between vector registers and general-purpose
registers with no conversions performed, so this is trivial to add
support for half-precision to.
 2020-04-22 20:58:11 +01:00
Lioncash
97dd3d0596 A64: Implement SQRDMULH's scalar indexed element variant 2020-04-22 20:58:11 +01:00
Lioncash
49b51e34f1 simd_vector_x_indexed_element: Deduplicate index and Vm operand construction 2020-04-22 20:58:11 +01:00
Lioncash
692aba91b6 A64: Implement SQDMULL{2}'s scalar indexed element variant 2020-04-22 20:58:11 +01:00
Lioncash
c043b831d5 A64: Implement SQDMULL{2}'s by-element variant 2020-04-22 20:58:11 +01:00
Lioncash
72af5a3dff simd_scalar_x_indexed_element: Factor out index and Vm argument construction 
This will be useful in the implementations of SQRDMULH and SQDMULL{2} as
well.
 2020-04-22 20:58:11 +01:00
Lioncash
224ff0afaa A64: Implement SQRDMULH's by-index vector variant 2020-04-22 20:58:11 +01:00
Lioncash
3a3542414b A64: Implement FRECPX's half-precision floating point variant 2020-04-22 20:58:11 +01:00
Lioncash
bd892ec4ef frontend/ir/ir_emitter: Amend FPRecipExponent to handle half-precision floating point 2020-04-22 20:58:11 +01:00
Lioncash
974fbf0677 frontend/ir/value: Add U16U32U64 type to represent floating point types 2020-04-22 20:58:11 +01:00
Lioncash
126c29a9e9 A64: Implement SQSHRN, SQSHRUN, and UQSHRN's scalar variants 
These can just be implemented in terms of the vector variants for the
time being.
 2020-04-22 20:58:11 +01:00
Lioncash
dd7433f9d3 A64: Amend prototypes of some SIMD scalar shift by immediate opcodes 
These take a vector for a destination.
 2020-04-22 20:58:11 +01:00
Merry
bbd5330ad2 Merge pull request #447 from lioncash/flag 
A64: Implement CFINV, RMIF, AXFlag and XAFlag
 2020-04-22 20:58:11 +01:00
Merry
fb039e232c Merge pull request #442 from lioncash/fcvtxn 
A64: Implement scalar and vector variants of FCVTXN
 2020-04-22 20:58:11 +01:00
Merry
4f937c1ee1 Merge pull request #446 from lioncash/sqshl 
A64: Implement scalar variants of SQSHL (register) and UQSHL (register)
 2020-04-22 20:58:11 +01:00
Lioncash
aa22db534b A64: Implement AXFlag and XAFlag 2020-04-22 20:58:11 +01:00
Merry
d74cccbc84 Merge pull request #445 from lioncash/sqrt 
A64: Implement single and double-precision vector variant of FSQRT
 2020-04-22 20:58:11 +01:00
Lioncash
20ffe568d0 A64: Implement RMIF 2020-04-22 20:58:11 +01:00
Merry
6d7e7c3269 Merge pull request #443 from lioncash/flag 
A64: Rearrange flag format/manipulation instructions
 2020-04-22 20:58:11 +01:00
Lioncash
51b526e453 A64: Implement CFINV 2020-04-22 20:58:11 +01:00
Lioncash
597a8be5d5 ir: Add A64-specific opcodes for getting and setting raw NZCV values 
This will be necessary to implement the flag manipulation and flag
format instructions.
 2020-04-22 20:58:11 +01:00
Lioncash
d3515279df A64: Implement the vector version of FCVTXN 2020-04-22 20:58:10 +01:00
Lioncash
17aea0b997 A64: Implement UQSHL (register)'s scalar variant 
This can be implemented in terms of the vector variant.
 2020-04-22 20:58:10 +01:00
Lioncash
c99d4b762e A64: Implement single and double-precision vector variant of FSQRT 2020-04-22 20:58:10 +01:00