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402 commits

Author SHA1 Message Date
Lioncash
67443efb62 General: Convert multiple namespace specifiers to nested namespace specifiers where applicable 
Makes namespacing a little less noisy
 2020-04-22 20:44:38 +01:00
MerryMage
d5283e46e8 IR: Implement IR instructions VectorEqual{8,16,32,64,128} 2020-04-22 20:44:38 +01:00
MerryMage
4ce9c65cfb reg_alloc: Use std::exchange 2020-04-22 20:44:38 +01:00
Fernando Sahmkow
e0c12ec2ad A64: Implemented EOR (vector), ORR (vector, register) and ORN (vector) Instructions (#142) 2020-04-22 20:44:38 +01:00
MerryMage
d124a1d761 emit_x64_packed: EmitPackedSubU16 modified xmm_b wasn't writeable 
For CPUs that didn't support SSE4.1, this was a bug.
 2020-04-22 20:44:38 +01:00
MerryMage
01a26fa644 fixup: travis: Test with disabled CPU feature detection 2020-04-22 20:44:37 +01:00
MerryMage
30936f5e94 travis: Test with disabled CPU feature detection 
Ensure that fallbacks are working correctly.
 2020-04-22 20:44:37 +01:00
MerryMage
285fd22c30 IR: Add IR instruction VectorZeroUpper 2020-04-22 20:44:37 +01:00
MerryMage
da3e9a5704 a64_emit_x64: bug: EmitA64WriteMemory128 should write not read 2020-04-22 20:44:37 +01:00
FernandoS27
ab84524806 Implemented SDIV and UDIV instructions 2020-04-22 20:44:37 +01:00
MerryMage
f698848e26 IR: Add IR instructions A64Memory{Read,Write}128 
Add the Windows ABI implementation
 2020-04-22 20:44:37 +01:00
MerryMage
e1df7ae621 IR: Add IR instructions A64Memory{Read,Write}128 
This implementation only works on macOS and Linux.
 2020-04-22 20:44:37 +01:00
MerryMage
e00a522cba IR: Add IR instruction VectorGetElement{8,16,32,64} 2020-04-22 20:44:37 +01:00
MerryMage
28ccd85e5c IR: Add IR instruction ZeroExtendToQuad 2020-04-22 20:44:37 +01:00
MerryMage
af848c627d block_of_code: Add ABI_RETURN2 2020-04-22 20:44:37 +01:00
MerryMage
1749780929 interface: Move Vector typedef to config.h 2020-04-22 20:44:37 +01:00
MerryMage
793753bf63 IR: Implement Vector{Lower,}Broadcast{8,16,32,64} 2020-04-22 20:44:37 +01:00
Lioncash
8ee854232c General: Default constructors and destructors where applicable 2020-04-22 20:44:37 +01:00
MerryMage
db30e02ac8 emit_x64: Extract BlockRangeInformation, remove template parameter 2020-04-22 20:44:36 +01:00
MerryMage
58c4a25527 emit_x64: Use JitStateInfo 2020-04-22 20:42:46 +01:00
MerryMage
eaf545877a IR: Implement Vector{Lower,}PairedAdd{8,16,32,64} 2020-04-22 20:42:46 +01:00
MerryMage
a554e4a329 backend_x64: Split emit_x64 2020-04-22 20:42:46 +01:00
Lioncash
b612782445 opcodes: Add 64-bit CountLeadingZeroes opcode 2020-04-22 20:42:46 +01:00
Lioncash
b08be71775 a32/a64_emit_x64: Remove unused includes 2020-04-22 20:42:46 +01:00
MerryMage
f81d0a2536 A64: Implement AND (vector) 2020-04-22 20:42:46 +01:00
MerryMage
a63fc6c89b A64: Implement ADD (vector, vector) 2020-04-22 20:42:46 +01:00
MerryMage
5eb0bdecdf IR: Simplify types. F32 -> U32, F64 -> U64, F128 -> U128 
ARM's Architecture Specification Language doesn't distinguish between floats and integers
as much as we do. This makes some things difficult to implement. Since our register
allocator is now capable of allocating values to XMMs and GPRs as necessary, the
Transfer IR instructions are no longer necessary as they used to be and they can be
removed.
 2020-04-22 20:42:46 +01:00
MerryMage
9a812b0c61 reg_alloc: GetBitWidth: Add UNREACHABLE 2020-04-22 20:42:46 +01:00
MerryMage
fff8e019dc reg_alloc: Consider bitwidth of data and registers when emitting instructions 2020-04-22 20:42:46 +01:00
MerryMage
6395f09f94 IR: Implement Conditional Select 2020-04-22 20:42:45 +01:00
MerryMage
19da68568e A64/translate/branch: bug: Read-after-write error in BLR 2020-04-22 20:42:45 +01:00
MerryMage
cdbc8d07a5 A64: Implement MOVN, MOVZ, MOVK 2020-04-22 20:42:45 +01:00
MerryMage
c6a091d874 A64: Optimization: Merge interpret blocks 2020-04-22 20:42:45 +01:00
MerryMage
996ffd5488 a64_emit_x64: bug: A64CallSupervisor trampled callee-save registers 2020-04-22 20:42:45 +01:00
MerryMage
e4615a4562 emit_x64: bug: OP m/r64, imm32 form instructions sign-extend their immediate on x64 2020-04-22 20:42:45 +01:00
MerryMage
0992987c98 A64: Add ExceptionRaised IR instruction 
The purpose of this instruction is to raise exceptions when certain decode-time
issues happen, instead of asserting at translate time. This allows us to
use the translator for code analysis without worrying about unnecessary asserts,
but also provides flexibility for the library user to perform custom behaviour
when one of these states are raised.
 2020-04-22 20:42:45 +01:00
MerryMage
aa74a8130b Misc. fixups of MSVC build 2020-04-22 20:42:45 +01:00
MerryMage
72a793f5b0 ir_opt: Split off A32 specific passes 2020-04-22 20:42:45 +01:00
MerryMage
243f06c613 A64: Implement LDP, STP 2020-04-22 20:42:45 +01:00
MerryMage
25411da838 A32: Implement load stores (immediate) 2020-04-22 20:42:45 +01:00
MerryMage
10c60dda97 a64_emit_x64: Don't use far code for now 2020-04-22 20:42:45 +01:00
MerryMage
593a569b53 EmitA64SetW: bug: should zero extend to entire 64-bit register 2020-04-22 20:42:45 +01:00
MerryMage
6bd9f02911 EmitA64SetNZCV: bug: to_store is scratch 2020-04-22 20:42:45 +01:00
MerryMage
f0276dd53b emit_x86: Fix nzcv for EmitSub 2020-04-22 20:42:45 +01:00
MerryMage
68391b0a05 A64: Implement SVC 2020-04-22 20:42:45 +01:00
MerryMage
e5ace37560 a64_emit_x64: Call interpreter 2020-04-22 20:42:45 +01:00
MerryMage
b12dead76a A64: Add batch register retrieval to interface 2020-04-22 20:42:45 +01:00
MerryMage
cb481a3a48 A64: Implement compare and branch 2020-04-22 20:42:45 +01:00
MerryMage
e8bcf72ee5 A64: PSTATE access and tests 2020-04-22 20:42:45 +01:00
MerryMage
23f3afe0b3 A64: Implement branch (register) 2020-04-22 20:42:45 +01:00
MerryMage
86d1095df7 A64: Implement branch 2020-04-22 20:42:45 +01:00
MerryMage
0641445e51 A64: Implement logical 2020-04-22 20:42:45 +01:00
MerryMage
5a1d88c5dc A64: Implement pcrel 2020-04-22 20:42:45 +01:00
MerryMage
c09e69bb97 A64: Implement addsub instructions 2020-04-22 20:42:44 +01:00
MerryMage
d1cef6ffb0 A64: Implement ADD_shifted 2020-04-22 20:42:44 +01:00
MerryMage
d1eb757f93 A64: Backend framework 2020-04-22 20:42:44 +01:00
MerryMage
83022322d1 Make IR->A32 LocationDescriptor conversion explicit 2020-04-22 20:39:27 +01:00
MerryMage
9d15e0a8e1 Final A32 refactor 2020-04-22 20:39:27 +01:00
MerryMage
455757d7b6 EmitX64: JitState type as template parameter 2020-04-22 20:39:26 +01:00
MerryMage
2d164d9345 Package up emit context 2020-04-22 20:38:31 +01:00
MerryMage
7bf421dd38 Rename JitState to A32JitState 2020-04-22 20:38:31 +01:00
MerryMage
63bd1ece23 backend_x64: Split A32 specific emission into separate class 2020-04-22 20:38:29 +01:00
MerryMage
8bef20c24d IR: Split off A32 specific opcodes 2020-04-22 20:33:32 +01:00
MerryMage
b1f0cf9278 A32: Split off A32 specific IREmitter 2020-04-22 20:33:32 +01:00
MerryMage
b3c73e2622 Label A32 specific code appropriately 2020-04-22 20:33:30 +01:00
MerryMage
dc357c780d EmitPackedHalvingSub{U,S}16: SSE2 implementation 2020-04-22 20:27:15 +01:00
MerryMage
a98821da41 Merge branch 'misc' 
These commits introduce context save and restore, and a small number of
optimizations that depend on their use for performance.
 2020-04-22 20:27:15 +01:00
MerryMage
fc885ac80f EmitPackedHalvingAddU8: Add SSE2 implementation 2020-04-22 20:27:15 +01:00
MerryMage
4682211729 EmitPackedHalvingAdd{U,S}16: Add SSE2 implementation 2020-04-22 20:27:15 +01:00
MerryMage
9ac1c87a51 emit_x64: EmitSet{Register,ExtendedRegister32,ExtendedRegister64}: Store from current source 2020-04-22 20:27:15 +01:00
MerryMage
6e834de072 Add re-entry prediction to avoid std::unordered_map lookups 2020-04-22 20:26:40 +01:00
MerryMage
984ce22431 emit_x64: Arguments to MostSignificantBit and IsZero are 32-bit 2020-04-22 20:26:40 +01:00
MerryMage
5c6fcf378f emit_x64: Optimize code emitted by EmitGetCpsr 2020-04-22 20:26:40 +01:00
MerryMage
f595f85039 block_of_code: Remove vzeroupper 2020-04-22 20:26:40 +01:00
MerryMage
4393473d06 interface: Allow saving and storing of contexts 2020-04-22 20:26:40 +01:00
MerryMage
05f3f07704 emit_x64: Reduce mxscr operations in EmitGetFpscr and EmitSetFpscr 2020-04-22 20:26:40 +01:00
MerryMage
19a7fb8992 jit_state: Split off CPSR.NZCV 2020-04-22 20:26:40 +01:00
MerryMage
a3432102b8 jit_state: Split off CPSR.Q 2020-04-22 20:26:40 +01:00
MerryMage
4f8675083c interface_x64: Fix MSVC cast warning 2020-04-22 20:26:40 +01:00
MerryMage
311361b409 jit_state: Split off CPSR.{E,T} 
This allows us to improve code-emission for PopRSBHint. We also improve
code emission other terminals at the same time.
 2020-04-22 20:26:40 +01:00
MerryMage
cb119c2f72 emit_x64: Use boost::icl::interval_map to speed up ranged invalidation 2020-04-22 20:26:40 +01:00
MerryMage
3cca3bbd0b jit_state: Split off CPSR.GE 2020-04-22 20:26:40 +01:00
MerryMage
6fde29f5d8 emit_x64: Remove unnecessary ABI overhead in ReadMemory, WriteMemory 2020-04-22 20:26:40 +01:00
MerryMage
6adc554b53 jit_state: Hide cpsr implementation 2020-04-22 20:26:40 +01:00
MerryMage
eb80aae9c0 block_of_code: Move MXCSR switching out of dispatch loop 
Also clarify MXCSR entry/exit terminology
 2020-04-22 20:26:40 +01:00
MerryMage
a4e85ad565 emit_x64: Make RSB a stack 2020-04-22 20:26:40 +01:00
MerryMage
2a818f9d8e Merge branch 'timing' 
We do this to improve timing information before entering a supervior
function. We also do this to try and stay within JITted code as much
as possible, by updating the cycles we have remaining.
 2020-04-22 20:26:37 +01:00
MerryMage
ea4c3292d5 BlockOfCode: Detect space remaining 
We also clear the code cache when we run out of space.

This closes #111.
 2020-04-22 20:26:12 +01:00
MerryMage
256749910f Add AddTicks and GetTicksRemaining callbacks 2020-04-22 20:26:12 +01:00
MerryMage
80c56aa89d Remove unnecessary use of boost::make_optional 
Closes #119.
 2020-04-22 20:26:12 +01:00
MerryMage
639f7cfd2d reg_alloc: Add IsLastUse optimization for UseScratch 2020-04-22 20:26:12 +01:00
MerryMage
6b122751fe reg_alloc: Remove reliance on IR::Inst::DecrementRemainingUses 2020-04-22 20:26:12 +01:00
MerryMage
30049ca928 emit_x86: Standardize time of DefineValue call 2020-04-22 20:26:12 +01:00
MerryMage
12eaf496fd emit_x64: Perform mask creation for packed instructions in SSE 2020-04-22 20:26:07 +01:00
MerryMage
305e4baa29 emit_x64: Eliminate conversion of GE flags 
* We do this so that we can simplify PackedSelect.
* We also try to minimise xmm-gpr/gpr-xmm transfers in PackedSelect.
 2020-04-22 20:26:07 +01:00
MerryMage
d1e0a29cd9 Implement IR instruction PackedSelect, reimplement SEL 2020-04-22 20:26:07 +01:00
MerryMage
18f11972c6 emit_x64: Remove SSSE3 implementation of PackedHalvingAddU8 
It is much slower than the SSE2 implementation, so there's no point keeping it around.
 2020-04-22 20:26:07 +01:00
MerryMage
c4b40909f7 emit_x64: Improve code emission of FPCompare{32,64} 
Replace if-chain with table lookup
 2020-04-22 20:26:07 +01:00
MerryMage
814e378249 VCMP and VCMPE were the other way around 
- This was due to a misunderstanding of what the E in VCMPE means.
- The E refers to an exception being raised when a QNaN is encountered.
- Added unit tests for VCMP{E}
 2020-04-22 20:26:07 +01:00
MerryMage
08f638d447 emit_x64: pmaxuw and pminuw require SSE 4.1 
This commit is intended to close citra-emu/citra#3137.

pmaxuw and pminuw were used to perform unsigned comparisons; we emulate
these using a signed comparison by offsetting the inputs by 0x8000 for
CPUs that do not support SSE 4.1.
 2020-04-22 20:26:07 +01:00