MerryMage
4e3675da7b
a64_merge_interpret_blocks: Remove debug output
2020-04-22 20:42:45 +01:00
MerryMage
c6a091d874
A64: Optimization: Merge interpret blocks
2020-04-22 20:42:45 +01:00
MerryMage
21fe61eac6
A64/data_processing_pcrel: bug: ADR{,P} instructions sign extend their immediate
2020-04-22 20:42:45 +01:00
MerryMage
7c4b70751c
A64/data_processing_addsub: bug: {ADD,SUB}S (extended register) instructions write to ZR when d = 31
2020-04-22 20:42:45 +01:00
MerryMage
996ffd5488
a64_emit_x64: bug: A64CallSupervisor trampled callee-save registers
2020-04-22 20:42:45 +01:00
MerryMage
e4615a4562
emit_x64: bug: OP m/r64, imm32 form instructions sign-extend their immediate on x64
2020-04-22 20:42:45 +01:00
MerryMage
0992987c98
A64: Add ExceptionRaised IR instruction
...
The purpose of this instruction is to raise exceptions when certain decode-time
issues happen, instead of asserting at translate time. This allows us to
use the translator for code analysis without worrying about unnecessary asserts,
but also provides flexibility for the library user to perform custom behaviour
when one of these states are raised.
2020-04-22 20:42:45 +01:00
MerryMage
61125d6dd1
A64/translate: Add TranslateSingleInstruction function
2020-04-22 20:42:45 +01:00
MerryMage
aa74a8130b
Misc. fixups of MSVC build
2020-04-22 20:42:45 +01:00
MerryMage
a1dfa01515
imm: Suppress MSVC warning C4244: value will never be truncated
2020-04-22 20:42:45 +01:00
MerryMage
26da149639
imm: compiler bug: MSVC 19.12 with /permissive- flag doesn't support fold expressions
2020-04-22 20:42:45 +01:00
MerryMage
b34c6616d4
A64/decoder: Split decoder data from header
2020-04-22 20:42:45 +01:00
MerryMage
72a793f5b0
ir_opt: Split off A32 specific passes
2020-04-22 20:42:45 +01:00
MerryMage
595f157e5e
A64: Implement LDP, STP
2020-04-22 20:42:45 +01:00
MerryMage
511215342b
A64/location_descriptor: Fix -fpermissive warning on GCC
2020-04-22 20:42:45 +01:00
MerryMage
243f06c613
A64: Implement LDP, STP
2020-04-22 20:42:45 +01:00
MerryMage
25411da838
A32: Implement load stores (immediate)
2020-04-22 20:42:45 +01:00
MerryMage
2aadeec291
A64: Implement SVC
2020-04-22 20:42:45 +01:00
MerryMage
9e27e4d250
imm: bug: SignExtend wasn't working for T with bit size > 32
2020-04-22 20:42:45 +01:00
MerryMage
10c60dda97
a64_emit_x64: Don't use far code for now
2020-04-22 20:42:45 +01:00
MerryMage
593a569b53
EmitA64SetW: bug: should zero extend to entire 64-bit register
2020-04-22 20:42:45 +01:00
MerryMage
6bd9f02911
EmitA64SetNZCV: bug: to_store is scratch
2020-04-22 20:42:45 +01:00
MerryMage
f0276dd53b
emit_x86: Fix nzcv for EmitSub
2020-04-22 20:42:45 +01:00
MerryMage
68391b0a05
A64: Implement SVC
2020-04-22 20:42:45 +01:00
MerryMage
e5ace37560
a64_emit_x64: Call interpreter
2020-04-22 20:42:45 +01:00
MerryMage
b12dead76a
A64: Add batch register retrieval to interface
2020-04-22 20:42:45 +01:00
MerryMage
cb481a3a48
A64: Implement compare and branch
2020-04-22 20:42:45 +01:00
MerryMage
e8bcf72ee5
A64: PSTATE access and tests
2020-04-22 20:42:45 +01:00
MerryMage
23f3afe0b3
A64: Implement branch (register)
2020-04-22 20:42:45 +01:00
MerryMage
86d1095df7
A64: Implement branch
2020-04-22 20:42:45 +01:00
MerryMage
0641445e51
A64: Implement logical
2020-04-22 20:42:45 +01:00
MerryMage
5a1d88c5dc
A64: Implement pcrel
2020-04-22 20:42:45 +01:00
MerryMage
c09e69bb97
A64: Implement addsub instructions
2020-04-22 20:42:44 +01:00
MerryMage
d1cef6ffb0
A64: Implement ADD_shifted
2020-04-22 20:42:44 +01:00
MerryMage
d1eb757f93
A64: Backend framework
2020-04-22 20:42:44 +01:00
MerryMage
e161cf16f5
A64: Initial framework
2020-04-22 20:42:44 +01:00
MerryMage
f61da0b5a9
IR: Compile-time type-checking of IR
2020-04-22 20:39:27 +01:00
MerryMage
44f7f04b5c
IR/Value: Rename RegRef and ExtRegRef to A32Reg and A32ExtReg
2020-04-22 20:39:27 +01:00
MerryMage
83022322d1
Make IR->A32 LocationDescriptor conversion explicit
2020-04-22 20:39:27 +01:00
MerryMage
9d15e0a8e1
Final A32 refactor
2020-04-22 20:39:27 +01:00
MerryMage
455757d7b6
EmitX64: JitState type as template parameter
2020-04-22 20:39:26 +01:00
MerryMage
2d164d9345
Package up emit context
2020-04-22 20:38:31 +01:00
MerryMage
7bf421dd38
Rename JitState to A32JitState
2020-04-22 20:38:31 +01:00
MerryMage
63bd1ece23
backend_x64: Split A32 specific emission into separate class
2020-04-22 20:38:29 +01:00
MerryMage
8bef20c24d
IR: Split off A32 specific opcodes
2020-04-22 20:33:32 +01:00
MerryMage
b1f0cf9278
A32: Split off A32 specific IREmitter
2020-04-22 20:33:32 +01:00
MerryMage
b3c73e2622
Label A32 specific code appropriately
2020-04-22 20:33:30 +01:00
MerryMage
dc357c780d
EmitPackedHalvingSub{U,S}16: SSE2 implementation
2020-04-22 20:27:15 +01:00
MerryMage
a98821da41
Merge branch 'misc'
...
These commits introduce context save and restore, and a small number of
optimizations that depend on their use for performance.
2020-04-22 20:27:15 +01:00
MerryMage
fc885ac80f
EmitPackedHalvingAddU8: Add SSE2 implementation
2020-04-22 20:27:15 +01:00
