bunnei
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691e4139fa
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arm: Implement B/BL/BX instructions.
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2016-08-03 16:49:01 -04:00 |
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Tillmann Karras
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fc33f1d374
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Implement more instructions
SXTB, SXTH, SXTAB, SXTAH, UXTB, UXTH, UXTAB, UXTAH, REV16
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2016-08-03 00:47:17 +01:00 |
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Tillmann Karras
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30a90295b9
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Implement data processing instructions
ADC, ADD, AND, BIC, CMN, CMP, EOR, MOV, MVN, ORR, RSB, RSC, SBC, SUB,
TEQ, TST
The code could use some serious deduplication...
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2016-08-03 00:47:16 +01:00 |
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MerryMage
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90d317b868
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Implement memory endianness. Implement Thumb SETEND instruction.
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2016-07-20 15:34:17 +01:00 |
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MerryMage
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98bd7ff6a5
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Decoder/Thumb16: Remove BL{,X} prefix/suffix decoders. We have 32-bit thumb instruction support.
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2016-07-20 12:08:17 +01:00 |
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Merry
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95316b8443
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Merged in Subv/dynarmic/arm_mem_tests (pull request #4)
Added some fuzz tests for most cases of ARM Load/Store instructions
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2016-07-20 10:19:55 +01:00 |
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MerryMage
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3f11a149d7
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Implement Thumb Instructions: BLX (imm), BL (imm)
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2016-07-18 22:18:58 +01:00 |
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MerryMage
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e0d6e28b67
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Implement Thumb instructions: BX, BLX (reg), B (T1), B (T2)
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2016-07-18 21:04:39 +01:00 |
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Subv
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ccc61472b9
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Added format strings for ARM STRBT encodings A1 and A2
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2016-07-18 14:20:58 -05:00 |
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Subv
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8617bf80a1
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Added format strings for ARM LDRBT encodings A1 and A2
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2016-07-18 14:18:39 -05:00 |
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Subv
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5d5ea9325c
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Added format strings for ARM STRT encodings A1 and A2
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2016-07-18 14:05:53 -05:00 |
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MerryMage
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2363759c62
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Implement thumb STM, LDM. Fix thumb POP implementation for P=1.
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2016-07-18 20:05:35 +01:00 |
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Subv
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77761ba032
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Added the format strings for LDRT encodings A1 and A2.
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2016-07-18 14:01:18 -05:00 |
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MerryMage
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14dcb18bbe
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Implemented Thumb Instructions: STR (imm, T1), STRB (imm), LDRB (imm), STR (imm, T2), LDR (imm, T2)
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2016-07-18 18:48:08 +01:00 |
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MerryMage
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a605a43ef9
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Implement Thumb Instructions: STRH (imm), LDRH (imm)
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2016-07-18 18:28:52 +01:00 |
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MerryMage
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f9755870bb
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Implement Thumb Instructions: LDR (reg), LDRH (reg), LDRSH (reg), LDRB (reg), LDRSB (reg)
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2016-07-18 18:02:02 +01:00 |
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MerryMage
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dfef65d98f
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Implement thumb POP instruction
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2016-07-18 17:37:48 +01:00 |
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MerryMage
|
f7e3d7b8d2
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Implement Thumb PUSH instruction
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2016-07-18 15:11:16 +01:00 |
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MerryMage
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9109b226af
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Implement Thumb instructions: ADD (SP plus imm, T1), ADD (SP plus imm, T2), SUB (SP minus imm)
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2016-07-18 11:16:12 +01:00 |
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MerryMage
|
c18a3eeab4
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Better MSVC support
* Avoiding use of templated variables.
* Now compling on MSVC with /WX (warnings as errors).
* Fixed all MSVC warnings.
* Fixed MSVC source_groups.
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2016-07-18 10:38:22 +01:00 |
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MerryMage
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bf99ddd065
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Merge branch 'master' of MerryMageBitbucket:MerryMage/dynarmic
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2016-07-18 10:33:52 +01:00 |
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MerryMage
|
28a201da16
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Implement Thumb ADR instruction
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2016-07-18 09:25:33 +01:00 |
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Subv
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0cdf5fe751
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Implemented ARM REV and REVSH instructions, with tests.
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2016-07-17 14:45:42 -05:00 |
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Merry
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24aa24b1bc
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Merged in Subv/dynarmic (pull request #1)
Implemented ARM CMP (imm) instruction.
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2016-07-17 19:43:49 +01:00 |
|
Subv
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7f09510945
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Implemented ARM CMP (imm) instruction.
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2016-07-17 13:29:37 -05:00 |
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MerryMage
|
3720da4e19
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Implement thumb16_{SXTH,SXTB,UXTH,UXTB,REV,REV16,REVSH}
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2016-07-16 19:23:42 +01:00 |
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MerryMage
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4b1c27e64f
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Implement arm_ADC_imm
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2016-07-14 20:02:41 +01:00 |
|
MerryMage
|
63242924fc
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Implement thumb16_SVC
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2016-07-14 15:01:30 +01:00 |
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MerryMage
|
9b2aff166a
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Implement arm_SVC
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2016-07-14 14:29:46 +01:00 |
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MerryMage
|
672ffb93d0
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frontend/translator: Skeleton for Arm translator
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2016-07-14 13:28:20 +01:00 |
|
MerryMage
|
8449deb0bc
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MSVC support
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2016-07-12 13:28:09 +01:00 |
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MerryMage
|
44352680c6
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s/thumb1/thumb16/g: Thumb16 refers to 16-bit thumb instructions, and Thumb32 to 32-bit ones
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2016-07-12 11:09:34 +01:00 |
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MerryMage
|
1410221b47
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Implement thumb1_STR_reg, thumb1_STRH_reg, thumb1_STRB_reg
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2016-07-11 23:11:05 +01:00 |
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MerryMage
|
e7922e4fef
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Implement thumb1_LDR_literal, thumb1_LDR_imm_t1
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2016-07-11 22:43:53 +01:00 |
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MerryMage
|
f0f14fa5e8
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Implement thumb1_MOV_reg
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2016-07-10 13:10:06 +08:00 |
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MerryMage
|
8920ce79b9
|
Implement thumb_CMP_reg_t2
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2016-07-10 12:23:16 +08:00 |
|
MerryMage
|
ac2fb6b925
|
Implement thumb1_MVN_reg
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2016-07-10 10:49:01 +08:00 |
|
MerryMage
|
d11df9067d
|
Implement thumb1_BIC_reg
|
2016-07-10 10:44:45 +08:00 |
|
MerryMage
|
98a64a92b1
|
Implement thumb1_ORR_reg
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2016-07-10 09:06:38 +08:00 |
|
MerryMage
|
3fe46d2c6f
|
Implement thumb1_CMN_reg
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2016-07-10 08:55:56 +08:00 |
|
MerryMage
|
641dbf8eb4
|
Implement thumb1_CMP_reg
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2016-07-10 08:52:28 +08:00 |
|
MerryMage
|
46408267c3
|
Implement thumb1_RSB_imm
|
2016-07-10 08:44:07 +08:00 |
|
MerryMage
|
6536ad9618
|
Implement thumb1_TST_reg
|
2016-07-10 08:35:58 +08:00 |
|
MerryMage
|
8145b33882
|
Implemented thumb1_ROR_reg
|
2016-07-10 08:18:17 +08:00 |
|
MerryMage
|
207cb74dc9
|
Implement thumb1_SBC_reg
|
2016-07-09 08:27:41 +08:00 |
|
MerryMage
|
1953e44532
|
Implement thumb1_ADC_reg
|
2016-07-08 22:17:39 +08:00 |
|
MerryMage
|
9e9fa62d5f
|
Implement thumb1_SUB_imm_t2
|
2016-07-08 21:48:55 +08:00 |
|
MerryMage
|
8c587df8ce
|
Implement thumb1_ADD_imm_t2
|
2016-07-08 21:38:43 +08:00 |
|
MerryMage
|
aa72323823
|
Implement thumb1_CMP_imm
|
2016-07-08 21:32:01 +08:00 |
|
MerryMage
|
98f300144b
|
Implement thumb1_MOV_imm
|
2016-07-08 21:27:27 +08:00 |
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