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Author SHA1 Message Date
Merry
0a232a6fbf emit_x64_vector_saturation: AVX2 implementation of EmitVectorUnsignedSaturatedAdd64 2021-05-28 15:34:49 +01:00
Wunkolo
57601f064b emit_x64_vector_saturation: AVX512 implementation of EmitVectorSignedSaturated 2021-05-28 15:34:49 +01:00
Wunkolo
332c26d432 emit_x64_vector_saturation: AVX512 implementation of VectorUnsignedSaturated{Add,Sub}{32,64} 2021-05-28 15:34:49 +01:00
Wunkolo
fa8cc1ac36 backend/x64: Add constants 
Used to redefine x86 assembly-constants without
including platform-dependent headers such as `immintrin.h`.

Currently includes vpcmp constants as well as ternary logic
utility-terms.

Removes `immintrin.h` requirement from emit_x64_vector_saturation
and updates our usage of `vpcmp` and `vpternlog` with the new constants
 2021-05-28 14:13:11 +01:00
Wunkolo
e8c266d0d3 tests/A64: Add VQADD/VQSUB unit tests 2021-05-28 14:13:11 +01:00
merry
8b4c73c833
README: Update readme 
- Add 'projects using' section
- Update guest architectures supported section
 2021-05-26 17:18:06 +01:00
MerryMage
6f87951178 externals: Remove unused submodule 2021-05-25 21:59:40 +01:00
MerryMage
f6f8024fb5 a32_emit_x64: Dump x64 disassembly upon fastmem patch failure 2021-05-25 21:57:29 +01:00
MerryMage
4256d21481 common: Add x64_disassemble 2021-05-25 21:56:59 +01:00
MerryMage
731c7fa4d9 externals: Build zydis 2021-05-25 21:32:34 +01:00
MerryMage
eed33f255d externals: Add zycore 
Merge commit '80d62f224900ab486a5bc5a6e80ce1e25a0e38e8' as 'externals/zycore'
 2021-05-25 21:28:58 +01:00
MerryMage
80d62f2249 Squashed 'externals/zycore/' content from commit 0c372cdef 
git-subtree-dir: externals/zycore
git-subtree-split: 0c372cdefe799e99812c008a0b74537bfa5fe077
 2021-05-25 21:28:55 +01:00
MerryMage
343b21ff7b externals: Add zydis 
Merge commit '6ee9beab3209bc301af98ee881bd15f0aeea2513' as 'externals/zydis'
 2021-05-25 21:23:45 +01:00
MerryMage
6ee9beab32 Squashed 'externals/zydis/' content from commit 25193db00 
git-subtree-dir: externals/zydis
git-subtree-split: 25193db008e8799ff59fd655c2a26b2ffd79d40d
 2021-05-25 21:23:39 +01:00
Mai M
fff4d9a4c7
Merge pull request #612 from Wunkolo/cpuinfo-concise 
cpu_info: Add CPU Name, Family, compact output
 2021-05-24 15:57:23 -04:00
Wunkolo
dc7fb1f3ed cpu_info: Add CPU Name, Family, compact output 
Compacts and formats the output a bit to be much more
concise. Sorts CPU features by alphabetical order. Mostly
to speed up `HostFeature` testing.
 2021-05-24 12:25:01 -07:00
MerryMage
17ae7f9ce1 IR: Implement IR instruction CallHostFunction 2021-05-23 15:44:57 +01:00
Wunkolo
3c693f2576 emit_x64_vector: AVX512VBMI implementation of EmitVectorTableLookup128 
Also adds AVX512VBMI detection to host_feature
 2021-05-22 22:48:31 +01:00
Wunkolo
37b24ee29e emit_x64_vector: AVX512{VL+BW} implementation of EmitVectorTableLookup128 
Based off of the SSE41 implementation but utilizing
embedded broadcasting, mask registers, and
the special zero-mask to default-initialize out-of-bound
indices to zero in the `is_defaults_zero` case.
 2021-05-22 22:47:21 +01:00
Wunkolo
9ba5e8e52d tests/A64: Add TBL/TBX instruction unit tests 
Tests the TBL instruction with implementation with {1-4} register
lookups and the handling of out-of-bound indices.
Intended to target the implementation of VectorTableLookup128
 2021-05-22 22:47:21 +01:00
MerryMage
53493b2024 Add .clang-format file 
Using clang-format version 12.0.0
 2021-05-22 15:07:02 +01:00
MerryMage
51b155df92 A32: Introduce PreCodeTranslationHook 2021-05-22 14:16:10 +01:00
Merry
714216fd0e Consolidate all source files into src/ directory 2021-05-19 17:41:59 +01:00
MerryMage
c6ecc835b6 ASIMD: Implement VCVT (between half-precision and single-precision) 2021-05-16 23:48:29 +01:00
MerryMage
d93145bd04 decoder_tests: Only run ASIMD decoder test explicitly 
The test is a 2 minute test whose result only really matters if the ASIMD decoder is modified.
 2021-05-16 21:48:25 +01:00
MerryMage
9de58f2875 assert: Check for unreachable code if DYNARMIC_IGNORE_ASSERTS isn't enabled 2021-05-16 21:46:44 +01:00
MerryMage
5bf74b5f04 reg_alloc: Determine size of spill slot with sizeof 2021-05-16 21:46:10 +01:00
MerryMage
b6bff56523 translate_thumb: Update current_instruction_size in TranslateSingleThumbInstruction 2021-05-16 10:31:30 +01:00
Wunkolo
2c0be5e18c emit_x64_vector: AVX512 Implementation of EmitVectorNarrow{32,64} 
Includes a new test case with the XTN instruction to verify
the implementation
 2021-05-16 10:02:49 +01:00
MerryMage
1643e8f3c6 translate_thumb: VFP/ASIMD conflict with coprocessor instructions 2021-05-15 20:54:35 +01:00
Wunkolo
105b464bc1 backend/x64: Implement HostFeature 2021-05-14 21:20:21 +01:00
MerryMage
b93ae62acf thumb32: Add coprocessor instructions 2021-05-13 18:15:35 +01:00
MerryMage
5ebe11c329 reg_alloc: Inform RegAlloc about rsp changes 2021-05-07 12:47:55 +01:00
MerryMage
05a6b5f623 translate_thumb: Permit ASIMD element or structure load/store instructions to be translated 2021-05-07 12:47:55 +01:00
MerryMage
62ecc2537e print_info: Add thumb mode 2021-05-07 08:24:51 +01:00
sunho
cb79bfa1dc thumb32: Support setflags in shift reg instructions 2021-05-05 11:47:49 +01:00
MerryMage
075fdeaee0 thumb32: Add Rn argument to ADD/SUB (Plain Binary Immediate) 2021-05-05 11:47:49 +01:00
MerryMage
ebe44dab7a stack_layout: Ignore warning C4324 for StackLayout 
We expect the structure to be padded
 2021-05-04 16:26:28 +01:00
MerryMage
462c884685 frontend/A32: Correct more IT state 2021-05-04 16:25:24 +01:00
MerryMage
c5f5c1d40f frontend: Standardize emitted IR for exception raising 2021-05-04 16:14:26 +01:00
MerryMage
3b2c6afdc2 backend/x64: Move cycles_remaining and cycles_to_run from JitState to stack 2021-05-04 14:40:13 +01:00
MerryMage
d6592c7142 Remove ExceptionalExit hack 2021-05-04 14:40:13 +01:00
MerryMage
030ff82ba8 backend/x64: Move check_bit from JitState to stack 2021-05-04 14:40:13 +01:00
MerryMage
a1950d1d2f backend/x64: Move save_host_MXCSR from JitState to stack 2021-05-04 14:19:05 +01:00
MerryMage
ddbc50cee0 backend/x64: Move spill from JitState onto the stack 2021-05-04 14:18:44 +01:00
MerryMage
f8d8ea0deb thumb32: Implement MRS (register) 2021-05-04 12:43:51 +01:00
MerryMage
61333917a4 thumb32: Implement MRS (register) 2021-05-04 12:43:38 +01:00
MerryMage
a5a210a9a5 T32: Add ASIMD instructions 2021-05-04 00:09:55 +01:00
MerryMage
d1e62b9993 T32: Add VFP instructions 2021-05-04 00:09:55 +01:00
MerryMage
cd837c5b37 A32: Merge ArmTranslateVistor and ThumbTranslateVisitor 2021-05-04 00:09:55 +01:00