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Author SHA1 Message Date
Lioncash
fab3a59e05 A32: Implement ARM-mode BFC 2020-04-22 21:02:46 +01:00
Merry
837c23a8ec Merge pull request #483 from lioncash/invert 
frontend/ir/cond: Remove unused invert() function
 2020-04-22 21:02:46 +01:00
Lioncash
7305d13221 A32: Implement ARM-mode RBIT 2020-04-22 21:02:46 +01:00
Lioncash
d12e375481 common/fp/op/FPConvert: Remove unnecessary casts in FPConvert() 
These were made unnecessary in 2c2fdb435cf8e358a0c5b907ce8131e434df3f22,
but were missed during the initial removal.
 2020-04-22 21:02:46 +01:00
Lioncash
b2f7a0e7ba A32: Implement ARM-mode SDIV/UDIV 
Now that we have Unicorn in place, we can freely implement instructions
introduced in newer versions of the ARM architecture.
 2020-04-22 21:02:46 +01:00
Lioncash
4f2b60c8e7 dynarmic_tests: Remove skyeye interpreter 
This is quite a messy interpreter and would require a large amount of
work to bring it up to speed to begin implementing newer portions of the
AArch32 instruction set into Dynarmic.

Given we already have fuzzing with Unicorn set up for
AArch64/AArch32, we can get rid of this and unify our testing
infrastructure.

This will also make building the tests much faster, given a whole
interpreter doesn't need to be built anymore as part of the project.
 2020-04-22 21:02:45 +01:00
Merry
09ee64ea98 Merge pull request #482 from lioncash/fixedfp 
A64: Handle half-precision variants of FP->Fixed instructions
 2020-04-22 21:02:45 +01:00
Lioncash
d29582a0e1 A32: Fuzz instructions using unicorn 
While skyeye was OK previously, now that we have an AArch64 backend,
this also means that we eventually have to support the AArch32
counterpart to it. Unfortunately, SkyEye is only compatible up to
ARMv6K, so we woud need to do a lot of work to bring the interpreter up
to speed with things to even begin testing new instruction
implementations.

For the AArch64 side of things, we already use Unicorn, so we can toss
out SkyEye in favor of it instead.
 2020-04-22 21:02:45 +01:00
MerryMage
1e1e9c17c7 emit_x64_data_processing: Remove INVALID_REG 
INVALID_REG.cvt8() now throws
 2020-04-22 21:02:45 +01:00
MerryMage
31a17c91c1 externals: Update xbyak to 73ac586 
Merge commit '76768f908381248e9ae32f4a4c82d3765ef2afa0' into HEAD
 2020-04-22 21:02:25 +01:00
MerryMage
76768f9083 Squashed 'externals/xbyak/' changes from 4a6fac8ad..73ac58660 
73ac58660 fix Reg::changeBit

git-subtree-dir: externals/xbyak
git-subtree-split: 73ac5866099b19bd8063f06434e19b9d7bbc9b8d
 2020-04-22 21:02:25 +01:00
Lioncash
06ec6ab0da frontend/ir/cond: Remove unused invert() function 
This is no longer used by anything in the codebase, so it can be
removed.
 2020-04-22 21:01:46 +01:00
Merry
d71f51b0da Merge pull request #481 from lioncash/alloc 
ir/basic_block: Forward declare headers where applicable
 2020-04-22 21:01:46 +01:00
Lioncash
64e3d233f4 A64: Handle half-precision variants of FP->Fixed-point instructions 2020-04-22 21:01:45 +01:00
Merry
2d3aa9b8fb Merge pull request #480 from lioncash/info 
common/fp/info: Make half-precision info struct functions return correctly sized types
 2020-04-22 21:01:45 +01:00
Lioncash
4fc531f71b ir/basic_block: Forward declare headers where applicable 
Now that the constructor and destructors have been placed within the cpp
file, we can forward declare the memory pool data structures. Now, a
change to the memory pool code won't ripple across the entirety of the
IR emitter.
 2020-04-22 21:01:45 +01:00
Lioncash
427b7afd66 frontend/ir/microinstruction: Add missing fixed-point opcodes to ReadsFromAndWritesToFPSRCumulativeExceptionBits() 2020-04-22 21:01:45 +01:00
Merry
699ad98b2a Merge pull request #479 from lioncash/rsqrts 
A64: Handle half-precision variants of FRSQRTS
 2020-04-22 21:01:45 +01:00
Lioncash
c9777ef997 common/fp/info: Make half-precision info struct functions return correctly sized types 
While initially done to potentially prevent creating bugs due to C++
having a silly type-promotion mechanism involving types < sizeof(int)
and unsignedness, given that the bulk of these functions' usages
are on exit paths, these can return the correct type to avoid the need
to cast at every usage point.
 2020-04-22 21:01:45 +01:00
Lioncash
9309d95b17 ir/block: Default ctor and dtor in the cpp file 
Prevents potentially inlining allocation code everywhere. While we're at
it, also explicitly delete/default the copy/move constructor/assignment
operators to be explicit about them.
 2020-04-22 21:01:45 +01:00
Lioncash
604f39f00a frontend/ir_emitter: Add half-precision->fixed-point opcodes 2020-04-22 21:01:45 +01:00
Lioncash
471eb77bc9 A64: Implement FRSQRTS' half-precision vector variant 2020-04-22 21:01:45 +01:00
Lioncash
4ecfbc14de common/fp/op/FPToFixed: Add half-precision specialization of FPToFixed 2020-04-22 21:01:45 +01:00
Lioncash
f9b2862217 A64: Implement FRSQRTS' half-precision scalar variant 
With the necessary machinery in place, we can now handle the
half-precision variant.
 2020-04-22 21:01:45 +01:00
Lioncash
96356fac93 frontend/ir_emitter: Add half-precision opcode variant of FPVectorRSqrtStepFused 2020-04-22 21:01:45 +01:00
Merry
45864133f5 Merge pull request #478 from lioncash/stepfused 
A64: Handle half-precision variants of FRECPE and FRECPS
 2020-04-22 21:01:44 +01:00
Lioncash
824c551ba2 frontend/ir_emitter: Add half-precision opcode variant of FPRSqrtStepFused 2020-04-22 21:01:44 +01:00
Merry
554c8c27c6 Merge pull request #477 from lioncash/rsqrt 
A64: Handle half-precision variants of FRSQRTE
 2020-04-22 21:01:44 +01:00
Lioncash
3739d92097 A64: Implement half-precision vector variant of FRECPE 2020-04-22 21:01:44 +01:00
Lioncash
e3b2eb57b5 common/fp/op/FPRSqrtStepFused: Add half-precision specialization for FPRSqrtStepFused 2020-04-22 21:01:44 +01:00
Merry
c6e6ec0e69 Merge pull request #476 from lioncash/frint 
A64: Handle half-precision variants of FRINT* instructions
 2020-04-22 21:01:44 +01:00
Lioncash
7b212ec8ae A64: Implement half-precision variant of FRSQRTE's vector variant 2020-04-22 21:01:44 +01:00
Lioncash
0945a491bd A64: Implement half-precision scalar variant of FRECPE 2020-04-22 21:01:44 +01:00
Merry
cb9a1b18b6 Merge pull request #475 from lioncash/muladd 
A64: Enable half-precision variants of floating-point multiply-add instructions
 2020-04-22 21:01:44 +01:00
Lioncash
d7f394fc1a A64: Enable half-precision vector FRINT* variants 2020-04-22 21:01:44 +01:00
Lioncash
77c84bcf9b A64: Implement half-precision variant of FRSQRTE's scalar variant 2020-04-22 21:01:44 +01:00
Lioncash
86b7626a2f A64: Implement half-precision vector variant of FRECPS 2020-04-22 21:01:44 +01:00
Merry
d6db7ad46c Merge pull request #474 from lioncash/bracing 
load_store_*: Make bracing consistent and variables const where applicable
 2020-04-22 21:01:44 +01:00
Merry
1b6520f5dd A64/location_descriptor: Ensure FZ16 is included in the FPCR mask 2020-04-22 21:01:44 +01:00
Lioncash
24f583c498 A64: Enable half-precision variants of floating-point FRINT* variants 
With all the backing machinery in place, we can remove the fallback
check for half-precision.
 2020-04-22 21:01:44 +01:00
Lioncash
037acb17b9 frontend/ir_emitter: Add half-precision opcode variant for FPVectorRSqrtEstimate 2020-04-22 21:01:44 +01:00
Lioncash
de43f011a7 A64: Implement half-precision scalar variant of FRECPS 2020-04-22 21:01:44 +01:00
Merry
13f421c27d Merge pull request #473 from lioncash/sqshlu 
A64: Implement SQSHLU
 2020-04-22 21:01:44 +01:00
Lioncash
b5bf890584 load_store_*: Make bracing consistent and variables const where applicable 
Makes bracing consistent, and variables const where applicable to be
consistent with the rest of the codebase.

In most bracing cases, they'd need to be added to conditionals that
would involve checking stack pointer alignment in the future anyways.
 2020-04-22 21:01:44 +01:00
Lioncash
9a58c3f1c7 A64: Implement FMLA/FMLS' half-precision vector indexed variants 2020-04-22 21:01:44 +01:00
Lioncash
fb829b9525 frontend/microinstruction: Add FPVectorRoundInt types to ReadsFromAndWritesToFPSRCumulativeExceptionBits() 
All variants were previously missing from this.
 2020-04-22 21:01:44 +01:00
Lioncash
5dba99b4f4 frontend/ir_emitter: Add half-precision opcode variant for FPRSqrtEstimate 2020-04-22 21:01:44 +01:00
Lioncash
825a3ea16f frontend/ir_emitter: Add half-precision opcode for FPVectorRecipEstimate 2020-04-22 21:01:44 +01:00
Merry
d7da53a74b Merge pull request #472 from lioncash/exception 
general: Mark hash functions as noexcept
 2020-04-22 21:01:44 +01:00
Lioncash
9dcc04e106 A64: Implement SQSHLU's scalar variant 2020-04-22 21:01:44 +01:00