219 commits

Author	SHA1	Message	Date
MerryMage	ca40015145	IR: Add Breakpoint IR instruction (for debugging purposes, emits a host-breakpoint)	2016-08-05 14:07:27 +01:00
Tillmann Karras	3fdc093d10	Add more IR opcodes for multiply instructions ... Pack2x32To1x64, LeastSignificantWord, MostSignificantWord, IsZero64, Add64, Mul, Mul64, SignExtendWordToLong, ZeroExtendWordToLong	2016-08-05 02:09:30 +01:00
Tillmann Karras	2488926341	Add IR opcode RotateRightExtended ... to rotate through the carry flag	2016-08-03 00:47:16 +01:00
MerryMage	be87038ffd	IROpt: Port get/set elimination pass to current IR	2016-08-02 11:51:05 +01:00
MerryMage	51448aa06d	More Speed	2016-07-22 23:55:00 +01:00
MerryMage	90d317b868	Implement memory endianness. Implement Thumb SETEND instruction.	2016-07-20 15:34:17 +01:00
MerryMage	3720da4e19	Implement thumb16_{SXTH,SXTB,UXTH,UXTB,REV,REV16,REVSH}	2016-07-16 19:23:42 +01:00
MerryMage	9b2aff166a	Implement arm_SVC	2016-07-14 14:29:46 +01:00
MerryMage	09420d190b	IR: Implement IR microinstructions ALUWritePC and LoadWritePC	2016-07-12 10:58:14 +01:00
MerryMage	1410221b47	Implement thumb1_STR_reg, thumb1_STRH_reg, thumb1_STRB_reg	2016-07-11 23:11:05 +01:00
MerryMage	e7922e4fef	Implement thumb1_LDR_literal, thumb1_LDR_imm_t1	2016-07-11 22:43:53 +01:00
MerryMage	d11df9067d	Implement thumb1_BIC_reg	2016-07-10 10:44:45 +08:00
MerryMage	98a64a92b1	Implement thumb1_ORR_reg	2016-07-10 09:06:38 +08:00
MerryMage	8145b33882	Implemented thumb1_ROR_reg	2016-07-10 08:18:17 +08:00
MerryMage	92142d5a22	Implement thumb1_SUB_reg	2016-07-08 18:49:30 +08:00
MerryMage	df0c324923	Implement thumb1_EOR_reg	2016-07-08 18:14:54 +08:00
MerryMage	8a0511d297	Implement thumb1_AND_reg	2016-07-08 17:44:53 +08:00
MerryMage	d0b48bfb59	Implement thumb1_ADD_reg_t1 and thumb1_ADD_reg_t2	2016-07-08 17:44:51 +08:00
MerryMage	d743adf518	Reorganisation, Import Skyeye, This is a mess	2016-07-04 17:22:11 +08:00

Renamed from src/frontend_arm/ir/opcodes.inc (Browse further)