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Author SHA1 Message Date
MerryMage
2524d536b0 A32/ir_emitter: Bugfix: ExceptionRaised was producing incorrect PC 
Use actual PC and not pipelined PC.
 2020-04-22 20:56:01 +01:00
Lioncash
c09f4cf28e constant_propagation_pass: Fold NOT operations 2020-04-22 20:55:50 +01:00
Lioncash
d69fceec55 value: Move ImmediateToU64() to be a part of Value's interface 
This'll make it slightly nicer to do basic constant folding for 32-bit
and 64-bit variants of the same IR opcode type. By that, I mean it's
possible to inspect immediate values without a bunch of conditional
checks beforehand to verify that it's possible to call GetU32() or
GetU64, etc.
 2020-04-22 20:55:50 +01:00
Lioncash
8013548bbb constant_propagation_pass: Fold OR operations 2020-04-22 20:55:50 +01:00
MerryMage
ca603c1215 reg_alloc: Emit AVX instructions where able 
Smaller codesize.
 2020-04-22 20:55:50 +01:00
Lioncash
898d096e39 constant_propagation_pass: Fold AND operations 2020-04-22 20:55:50 +01:00
MerryMage
e2358af5ef abi: Emit AVX instructions where able 
Smaller codesize.
 2020-04-22 20:55:50 +01:00
Lioncash
f40fcda1f6 ir/value: Add member function to check whether or not all bits of a contained value are set 
This is useful when we wish to know if a contained value is something
like 0xFFFFFFFF, as this helps perform constant folding. For example the
operation: x & 0xFFFFFFFF can be folded to just x in the 32-bit case.
 2020-04-22 20:55:50 +01:00
MerryMage
7c0378f56d a64_exclusive_monitor: Loosen memory ordering requirements 
It is not necessary to be as strict as it was.
 2020-04-22 20:55:50 +01:00
Lioncash
0ea99b7d59 constant_propagation_pass: Fold EOR operations 
It's possible to fold cases of exclusive OR operations if they can be
known to be an identity operation, or if both operands happen to be known
immediates, in which case we can just store the result of the
exclusive-OR directly.
 2020-04-22 20:55:50 +01:00
Lioncash
6e3e251031 travis: Make macOS builds use Xcode 10 
Keeps the toolchain up to date and allows the use of things like
<optional> and <variant> from the standard library.
 2020-04-22 20:55:50 +01:00
MerryMage
f0920c0ded Fix VShift terminology 
An arithmetic shift is by definition a signed shift, and a logical shift is by definition an unsigned shift.

- Rename VectorLogicalVShiftS* -> VectorArithmeticVShift*
- Rename VectorLogicalVShiftU* -> VectorLogicalVShift*
 2020-04-22 20:55:50 +01:00
MerryMage
b51dae790d emit_x64_vector: AVX512 implementation of EmitVectorLogicalVShiftS16 2020-04-22 20:55:50 +01:00
MerryMage
bd47f2ca8f emit_x64_vector: AVX512 implementation of EmitVectorLogicalVShiftS64 2020-04-22 20:55:50 +01:00
MerryMage
3bf183d7e8 emit_x64_vector: AVX2 implementation of EmitVectorLogicalVShiftS32 2020-04-22 20:55:50 +01:00
MerryMage
94f9d402eb emit_x64_vector: AVX512 implementation of EmitVectorLogicalVShiftU16() 2020-04-22 20:55:50 +01:00
MerryMage
6d9639e3b0 emit_x64_vector: AVX2 implementation of EmitVectorLogicalVShiftU64() 2020-04-22 20:55:50 +01:00
MerryMage
bbc066a266 emit_x64_vector: AVX2 implementation of EmitVectorLogicalVShiftU32() 2020-04-22 20:55:50 +01:00
Lioncash
da2e7fad87 emit_x64_vector: SSSE3 variant of EmitVectorCountLeadingZeros8() 
pshufb lyfe
 2020-04-22 20:55:50 +01:00
Mat M
9130ed45b9 Merge pull request #397 from VelocityRa/dec-shift-fix 
decoders: Cast to correctly-sized type before shifting
 2020-04-22 20:55:50 +01:00
MerryMage
238f2f2cd0 a64_emit_x64: Lowercase PAGE_SIZE 
PAGE_SIZE is defined as a macro by musl.
 2020-04-22 20:55:50 +01:00
VelocityRa
c30b8dbe99 decoders: Cast to correctly-sized type before shifting 
Fixes decoding for 64-bit instructions

Does not help/apply to any currently supported ARM versions (since
all are 32-bit length or below), it's for future-proofing should
such an arch be supported.
 2020-04-22 20:55:50 +01:00
MerryMage
7162f6f254 emit_x64_vector_floating_point: SSE4.1 implementation of EmitFPVectorToFixed 2020-04-22 20:55:50 +01:00
MerryMage
e7a5592699 emit_x64_vector_floating_point: EmitFPVectorRoundInt: Use FCODE 2020-04-22 20:55:50 +01:00
MerryMage
b8fde48732 emit_x64_vector: AVX implementation for EmitVectorCountLeadingZeros8 2020-04-22 20:55:50 +01:00
MerryMage
fd37b637aa emit_x64_vector: SSE implementation of EmitVectorCountLeadingZeros16 2020-04-22 20:55:50 +01:00
MerryMage
09bf273bc8 A64: Implement SCVTF, UCVTF (vector, fixed-point), scalar variant 2020-04-22 20:55:06 +01:00
MerryMage
03ad2072a7 emit_x64_floating_point: Reduce fallback LUT code in EmitFPToFixed 2020-04-22 20:55:06 +01:00
MerryMage
f9129db6fd A64: Implement FCVTZS, FCVTZU, UCVTF, SCVTF (vector, fixed-point), vector variant 2020-04-22 20:55:06 +01:00
Lioncash
48df9b9a7d A64: Implement UQSHL's vector immediate and register variants 2020-04-22 20:55:06 +01:00
Lioncash
d426dfe942 ir: Add opcodes for unsigned saturating left shifts 2020-04-22 20:55:06 +01:00
Lioncash
ab60720418 A64/translate/impl: Make signatures consistent for unimplemented by-element SIMD variants 
Makes them all consistent, so it isn't necessary to change the
prototypes over when implementing them.
 2020-04-22 20:55:06 +01:00
Lioncash
6b5ea6ee66 A64: Implement BRK 
Currently, we can just implement this as part of the exception
interface, similar to how it's done for the A32 interface with BKPT.
 2020-04-22 20:55:06 +01:00
Lioncash
b915364c16 A64/imm: Add full range of comparison operators to Imm template 
Makes the comparison interface consistent by providing all of the
relevant members. This also modifies the comparison operators to take
the Imm instance by value, as it's really only a u32 under the covers,
and it's cheaper to shuffle around a u32 than a 64-bit pointer address.
 2020-04-22 20:55:06 +01:00
MerryMage
02150bc0b7 IR: Add fbits argument to FPVectorFrom{Signed,Unsigned}Fixed 2020-04-22 20:55:06 +01:00
MerryMage
027b0ef725 A64: Implement SCVTF, UCVTF (scalar, fixed-point) 2020-04-22 20:55:06 +01:00
MerryMage
8051f60db0 opcodes.inc: Align columns to a tabstop of 4 2020-04-22 20:55:06 +01:00
MerryMage
90193b0e3d IR: Add fbits argument to FixedToFP-related opcodes 2020-04-22 20:55:06 +01:00
Lioncash
616a153c16 A64: Implement SQSHL's vector immediate variant 2020-04-22 20:55:06 +01:00
Lioncash
e8b0f25dff A64: Implement SQSHL's vector register variant 2020-04-22 20:55:06 +01:00
Lioncash
b14eaaec46 ir: Add opcodes for left signed saturated shifts 2020-04-22 20:55:06 +01:00
Lioncash
da55ed7b31 branch: Make variables const where applicable 2020-04-22 20:55:06 +01:00
Lioncash
867b666285 move_wide: Make variables const where applicable 2020-04-22 20:55:06 +01:00
Lioncash
78024a9dc4 load_store_register_unprivileged: Make variables const where applicable 2020-04-22 20:55:06 +01:00
Lioncash
e45e5da610 load_store_register_immediate: Place conditional bodies on their own line 
Makes the conditionals visually consistent with the rest of the
codebase.
 2020-04-22 20:55:06 +01:00
Lioncash
b586cf3f56 load_store_load_literal: Make variables const where applicable 2020-04-22 20:55:06 +01:00
Lioncash
c3a3b9687e data_processing_logical: Move datasize declarations after early-exit conditionals 
While we're at it, make variables const where applicable.
 2020-04-22 20:55:06 +01:00
Lioncash
ed797e6540 data_processing_conditional_select: Make variables const where applicable 
Makes CSEL's function consistent with all of the others.
 2020-04-22 20:55:06 +01:00
Lioncash
c82fa5ec5a data_processing_addsub: Move datasize declarations after early-exit conditionals 
While we're at it, also make relevant variables const where applicable
 2020-04-22 20:55:06 +01:00
Lioncash
f4a66d2477 data_processing_bitfield: Move datasize variables after early-exit conditionals 
Moves the declaration of datasize to the scope that it's used within.
This also takes the opportunity to apply const where applicable, and
make early-exits all vertically consistent with one another.
 2020-04-22 20:55:06 +01:00