MerryMage
|
589d717af5
|
A32: Implement ASIMD VQRSHRUN
|
2020-06-21 17:41:18 +01:00 |
|
MerryMage
|
e009d99924
|
A32: Implement ASIMD VSHRN
|
2020-06-21 17:41:18 +01:00 |
|
MerryMage
|
473949d486
|
asimd_load_store_structures: Suppress MSVC shift warning
|
2020-06-21 17:41:18 +01:00 |
|
MerryMage
|
8f0f1cfd66
|
A32: Implement ASIMD VST{1,2,3,4} (single n-element structure from one lane)
|
2020-06-21 16:27:33 +01:00 |
|
MerryMage
|
fa145ae401
|
a32_unicorn: Print code on unicorn error
|
2020-06-21 16:23:01 +01:00 |
|
MerryMage
|
5a597f415c
|
A32: Implement A32 VLD{1,2,3,4} (single n-element structure to one lane)
|
2020-06-21 16:22:43 +01:00 |
|
MerryMage
|
f221912409
|
bit_util: Bits without template arguments
|
2020-06-21 16:07:59 +01:00 |
|
MerryMage
|
3202e4c539
|
A32: Implement ASIMD VLD{1,2,3,4} (single n-element structure to all lanes)
|
2020-06-21 15:25:26 +01:00 |
|
MerryMage
|
d7197745ac
|
emit_x64_vector_floating_point: fpcr_controlled is unused when fsize == 16 in EmitFPVectorToFixed
|
2020-06-21 14:46:06 +01:00 |
|
MerryMage
|
b32fc5ab0f
|
a64_emit_x64: EmitVAddrLookup: Use bzhi instruction when silently_mirror_page_table is active and BMI2 is available
|
2020-06-21 14:46:06 +01:00 |
|
MerryMage
|
809dfe9c54
|
A32: Implement ASIMD VCVT (between floating-point and integer)
|
2020-06-21 14:28:25 +01:00 |
|
MerryMage
|
43a4b2a0b8
|
ir_emitter: Remove dummy fpcr_controlled arguments from scalar FP instructions
|
2020-06-21 14:28:25 +01:00 |
|
MerryMage
|
c836b389c8
|
emit_x64_vector_floating_point: Add fpcr_controlled argument to all IR instructions
|
2020-06-21 14:28:25 +01:00 |
|
MerryMage
|
33a81dae68
|
asimd: VEXT was being shadowed
|
2020-06-21 13:12:19 +01:00 |
|
MerryMage
|
bf093395d8
|
A32: Implement ASIMD VMOVN
|
2020-06-21 12:35:39 +01:00 |
|
MerryMage
|
c7785cd982
|
A32: Implement ASIMD VUZP and VZIP
|
2020-06-21 12:34:55 +01:00 |
|
MerryMage
|
603cd09c8f
|
A32: Implement ASIMD VTRN
|
2020-06-21 12:14:13 +01:00 |
|
MerryMage
|
a8b481ab63
|
simd_permute: Implement TRN{1,2} in terms of VectorTranspose
|
2020-06-21 12:14:13 +01:00 |
|
MerryMage
|
7d1e103ff5
|
IR: Implement VectorTranspose
|
2020-06-21 12:14:13 +01:00 |
|
MerryMage
|
9cc11681dc
|
A32: Implement ASIMD VMLAL, VMLSL, VMULL (scalar)
|
2020-06-21 10:31:30 +01:00 |
|
MerryMage
|
69a1d58a2b
|
A32: Implement ASIMD VMULL
|
2020-06-21 10:00:24 +01:00 |
|
Lioncash
|
8c23f02330
|
A32: Implement ASIMD VABD
|
2020-06-21 07:54:21 +01:00 |
|
Lioncash
|
fc1633a2ea
|
A32: Implement ASIMD VABA
|
2020-06-21 07:54:21 +01:00 |
|
Lioncash
|
bdb92f7055
|
asimd: Split out VABA/VABD decoders
These differ in bit encodings anyway
|
2020-06-21 07:54:21 +01:00 |
|
Lioncash
|
230fa02648
|
A32: Implement ASIMD VMLA/VMLS (scalar)
While we're at it, we can join the implementation of VMUL into a common
function.
|
2020-06-21 07:51:17 +01:00 |
|
MerryMage
|
70d071e6ab
|
fuzz_arm: Test large random blocks
|
2020-06-21 00:41:54 +01:00 |
|
MerryMage
|
239ee289cf
|
A32: Implement VDUP (scalar)
|
2020-06-21 00:22:42 +01:00 |
|
Lioncash
|
a8efe3f0f5
|
A32: Implement ASIMD VACGE/VACGT
|
2020-06-21 00:02:48 +01:00 |
|
Lioncash
|
e319257ec0
|
A32: Implement VCEQ/VCGE/VCGT (floating point)
|
2020-06-21 00:02:48 +01:00 |
|
Lioncash
|
faefb264a6
|
A32: Implement ASIMD VCEQ (integer)
|
2020-06-21 00:02:48 +01:00 |
|
Lioncash
|
7276993352
|
A32: Implement ASIMD VCGE (integer)
|
2020-06-21 00:02:48 +01:00 |
|
Lioncash
|
7292320445
|
A32: Implement ASIMD VCGT (integer)
|
2020-06-21 00:02:48 +01:00 |
|
MerryMage
|
fda4e11887
|
A32: Implement ASIMD VMOV (general-purpose register to scalar)
|
2020-06-20 23:40:48 +01:00 |
|
MerryMage
|
7ec22b4e1d
|
A32: Implement ASIMD VMOV (scalar to general-purpose register)
|
2020-06-20 23:30:56 +01:00 |
|
MerryMage
|
8bbc9fdbb6
|
A32: Implement ASIMD VTBX
|
2020-06-20 22:35:31 +01:00 |
|
Lioncash
|
06f7229c57
|
A32: Implement ASIMD VPADAL (integer)
|
2020-06-20 22:28:47 +01:00 |
|
Lioncash
|
266c6a2000
|
A32: Implement ASIMD VPADDL (integer)
|
2020-06-20 22:28:47 +01:00 |
|
Lioncash
|
4bb286ac23
|
A32: Implement ASIMD VPADD (integer)
|
2020-06-20 21:22:14 +01:00 |
|
Lioncash
|
1ffeeeb6a2
|
A32: Implement ASIMD VMAX/VMIN (integer)
|
2020-06-20 21:20:47 +01:00 |
|
Lioncash
|
945b757b6c
|
A32: Implement ASIMD VMLA/VMLS (integer)
|
2020-06-20 21:20:21 +01:00 |
|
MerryMage
|
715db8381f
|
A32: Implement ASIMD VMUL (scalar)
|
2020-06-20 20:34:08 +01:00 |
|
MerryMage
|
b0beecdd41
|
A32: Implement ASIMD VTBL
|
2020-06-20 19:25:14 +01:00 |
|
MerryMage
|
28f27bc19d
|
A32: Implement ASIMD VEXT
|
2020-06-20 19:05:14 +01:00 |
|
MerryMage
|
e8c460c167
|
A32: Implement ASIMD VDUP (ARM core register)
|
2020-06-20 16:02:43 +01:00 |
|
MerryMage
|
15ee562dd0
|
decoder/asimd: Add misc data-processing instructions
|
2020-06-20 15:39:00 +01:00 |
|
MerryMage
|
214c1d6002
|
fuzz_arm: Test testable parts of ASIMD VRECPE and VRSQRTE
|
2020-06-20 15:17:39 +01:00 |
|
MerryMage
|
92cb4a5a34
|
A32: Implement ASIMD VRSQRTE
|
2020-06-20 15:13:22 +01:00 |
|
MerryMage
|
8912496206
|
fuzz_arm: Unicorn has incorrect VRSQRTS implementation
|
2020-06-20 15:07:50 +01:00 |
|
MerryMage
|
6f59c2cd8e
|
A32: Implement ASIMD VRECPE
|
2020-06-20 15:07:06 +01:00 |
|
MerryMage
|
d3dc50d718
|
A32: Implement ASIMD VRSQRTS
|
2020-06-20 15:06:06 +01:00 |
|