Merry
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cd1eef2801
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Merged in bunnei/dynarmic/load_store (pull request #9)
arm: Implement LDR/LDRB/LDRH/LDRD/STR/STRB/STRH/STRD.
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2016-08-06 14:22:45 +01:00 |
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bunnei
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2448d52394
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load_store: Use correct types for LDR/STR.
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2016-08-05 20:51:32 -04:00 |
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bunnei
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8c2300d477
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arm: Implement LDRD reg/imm instructions.
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2016-08-05 20:05:02 -04:00 |
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bunnei
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72608b7af6
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arm: Handle Cond::NV (some 3DS games use this despite being obsolete).
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2016-08-05 20:05:02 -04:00 |
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bunnei
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ec3a98cf95
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arm: Implement LDRH reg/imm instructions.
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2016-08-05 20:05:01 -04:00 |
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bunnei
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192a0fba7a
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arm: Implement LDRB reg/imm instructions.
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2016-08-05 20:05:00 -04:00 |
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bunnei
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dfb318f208
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arm: Implement STRD reg/imm instructions.
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2016-08-05 20:04:59 -04:00 |
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bunnei
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e931dc2496
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arm: Implement STRH reg/imm instructions.
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2016-08-05 20:04:58 -04:00 |
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bunnei
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9f77662b24
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arm: Implement STRB reg/imm instructions.
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2016-08-05 20:04:57 -04:00 |
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bunnei
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a5e2116e12
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fuzz_arm: Log write records on failure.
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2016-08-05 20:04:57 -04:00 |
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bunnei
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caab1bbc7c
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arm: Implement STR reg/imm instructions.
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2016-08-05 20:04:56 -04:00 |
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bunnei
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b09ecb4532
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arm: Implement LDR reg/imm instructions.
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2016-08-05 20:04:55 -04:00 |
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MerryMage
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856298577d
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EmitX64: Don't give MOVSX or MOVZX an immediate oparg
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2016-08-06 01:03:39 +01:00 |
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MerryMage
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640ce48baa
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VFP: Implement {Get,Set}ExtendedRegister{32,64}
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2016-08-05 19:06:10 +01:00 |
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MerryMage
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d31bbd6d14
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Common/x64/CpuDetect: Disable MSVC warning for strncpy
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2016-08-05 18:44:01 +01:00 |
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MerryMage
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4c0a85f3b3
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EmitX64: Correct EmitPack2x32To1x64 implementation
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2016-08-05 18:43:24 +01:00 |
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MerryMage
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742eeb8913
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BackendX64/RegAlloc: Correct debugging asserts and correct UseDef behaviour for spill locations
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2016-08-05 18:43:22 +01:00 |
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MerryMage
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d2aeb56503
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Common: DEBUG_ASSERTs weren't enabled
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2016-08-05 18:43:21 +01:00 |
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MerryMage
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6f6f60c61b
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tests/FuzzArm: Only call raise(SIGTRAP) when __unix__ is defined
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2016-08-05 16:04:16 +01:00 |
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MerryMage
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d80dcc5367
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BackendX64/EmitX64: Eliminate unnecessary MOVs in Add64, Mul, Mul64, SignExtendWordToLong, ZeroExtendWordToLong, Pack2x32To1x64
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2016-08-05 15:27:29 +01:00 |
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MerryMage
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2b025183a2
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BackendX64/RegAlloc: Correct UseDefRegsiter behaviour for last use
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2016-08-05 15:24:25 +01:00 |
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MerryMage
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b4aa01ccf4
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Merge remote-tracking branch 'tilkax/master'
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2016-08-05 14:14:06 +01:00 |
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MerryMage
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94e75ad32f
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BackendX64/EmitX64: Reduce number of MOVs by using reg_alloc.{RegisterAddDef,UseDefOpArg,UseOpArg}
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2016-08-05 14:11:27 +01:00 |
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MerryMage
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92bd5f214b
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BackendX64/RegAlloc: Add RegisterAddDef, UseDefOpArg, UseOpArg
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2016-08-05 14:10:39 +01:00 |
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MerryMage
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01cfaf0286
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IR: Properly support Identity in IR::Value
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2016-08-05 14:09:10 +01:00 |
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MerryMage
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ca40015145
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IR: Add Breakpoint IR instruction (for debugging purposes, emits a host-breakpoint)
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2016-08-05 14:07:27 +01:00 |
|
Tillmann Karras
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fce8c86c90
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Implement RSB
somehow missed this earlier
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2016-08-05 02:13:26 +01:00 |
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Tillmann Karras
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eb2e6e8bea
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Implement some multiplies
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2016-08-05 02:09:54 +01:00 |
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Tillmann Karras
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72c503016c
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Fix Pack2x32To1x64
Not sure how to fix this properly.
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2016-08-05 02:09:30 +01:00 |
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Tillmann Karras
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3fdc093d10
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Add more IR opcodes for multiply instructions
Pack2x32To1x64, LeastSignificantWord, MostSignificantWord, IsZero64,
Add64, Mul, Mul64, SignExtendWordToLong, ZeroExtendWordToLong
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2016-08-05 02:09:30 +01:00 |
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Tillmann Karras
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a97668ead4
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Simplify ARM fuzz tests
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2016-08-05 02:09:30 +01:00 |
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Tillmann Karras
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023643b4fa
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Disable load/store tests for now
I don't feel like debugging that right now.
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2016-08-05 02:09:27 +01:00 |
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Tillmann Karras
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ab383b4be5
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Break tests by fixing them
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2016-08-05 02:08:41 +01:00 |
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Tillmann Karras
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af27ef8d6c
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Optionally disassemble x86_64 code using LLVM
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2016-08-05 02:08:41 +01:00 |
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Merry
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39563c8ea8
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Merged in bunnei/dynarmic (pull request #8)
arm: Implement B/BL/BX instructions.
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2016-08-04 13:22:00 +01:00 |
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bunnei
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691e4139fa
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arm: Implement B/BL/BX instructions.
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2016-08-03 16:49:01 -04:00 |
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Tillmann Karras
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fc33f1d374
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Implement more instructions
SXTB, SXTH, SXTAB, SXTAH, UXTB, UXTH, UXTAB, UXTAH, REV16
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2016-08-03 00:47:17 +01:00 |
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Tillmann Karras
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30a90295b9
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Implement data processing instructions
ADC, ADD, AND, BIC, CMN, CMP, EOR, MOV, MVN, ORR, RSB, RSC, SBC, SUB,
TEQ, TST
The code could use some serious deduplication...
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2016-08-03 00:47:16 +01:00 |
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Tillmann Karras
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fe71cc9d78
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Disassemble reg-shifted regs in lower case
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2016-08-03 00:47:16 +01:00 |
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Tillmann Karras
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2488926341
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Add IR opcode RotateRightExtended
to rotate through the carry flag
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2016-08-03 00:47:16 +01:00 |
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Tillmann Karras
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dacaeadb6a
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Raise SIGTRAP on non-Windows
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2016-08-03 00:44:08 +01:00 |
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Tillmann Karras
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306e070ab5
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Use opcodes.inc for emit_x64.h
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2016-08-03 00:44:08 +01:00 |
|
Tillmann Karras
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61eddbd1fa
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Fix Linux build
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2016-08-03 00:44:08 +01:00 |
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MerryMage
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1252bd653d
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RegAlloc: Define constructors for HostLocInfo to make MSVC happy
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2016-08-03 00:25:42 +01:00 |
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MerryMage
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a875c0c720
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TranslateArm: Stub more ARM instructions
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2016-08-02 21:59:33 +01:00 |
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MerryMage
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64c17a2489
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tests/FuzzArm: Print out IR upon failure
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2016-08-02 13:48:06 +01:00 |
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MerryMage
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deb5e2c10d
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IR::DumpBlock: Incorrect use of std::map::at
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2016-08-02 13:47:05 +01:00 |
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MerryMage
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4414ec5bc8
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RegAlloc: Allow allocation of XMM registers
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2016-08-02 13:46:12 +01:00 |
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MerryMage
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864081d1a0
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BackendX64: ArithmeticShiftRight: Fix incorrect immediate size for SAR
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2016-08-02 12:00:11 +01:00 |
|
MerryMage
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6097a21955
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TranslateArm: Reorganisation - Split visitor into multiple .cpp files
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2016-08-02 11:54:04 +01:00 |
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