Merry
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868bd00ab5
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A32: Rearrange translators for ASIMD Three Registers
* Separate Three Registers with Different Lengths from Same Lengths decoders
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2020-06-27 11:15:07 +01:00 |
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Merry
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b1ff971a92
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backend/x64: Temporarily avoid use of DefineValue(Argument&)
Issues with inappropriate values in upper bits of values
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2020-06-27 10:52:59 +01:00 |
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Merry
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337498823c
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FindUnicorn: Fix find_package_handle_standard_args warning
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2020-06-27 10:06:39 +01:00 |
|
MerryMage
|
8a1f106dba
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decoder/asimd: Correct names of scalar exceptions
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2020-06-25 17:40:11 +01:00 |
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MerryMage
|
495f58eed8
|
A32: Implement ASIMD VSHLL
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2020-06-24 23:47:13 +01:00 |
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MerryMage
|
ed48a9d7d5
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A32: Implement VFPv5 VRINTX
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2020-06-24 22:31:58 +01:00 |
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MerryMage
|
46445d0866
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A64: Remove NaN accuracy setting
Always do accuracte NaN handling.
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2020-06-24 22:26:10 +01:00 |
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Lioncash
|
b5df8d1ef8
|
A32: Implement ASIMD VQDMULL (scalar)
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2020-06-23 18:19:42 +01:00 |
|
Lioncash
|
20a2bf29fc
|
A32: Implement ASIMD VQRDMULH (scalar)
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2020-06-23 18:19:42 +01:00 |
|
Lioncash
|
ab5efe8632
|
A32: Implement ASIMD VQDMULH (scalar)
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2020-06-23 18:19:42 +01:00 |
|
MerryMage
|
2008fda88b
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emit_x64_floating_point: Correct error in s16 rounding in EmitFPToFixed
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2020-06-22 22:54:38 +01:00 |
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MerryMage
|
3ea49fc6d6
|
A32: Implement VFPv3 VCT (between floating-point and fixed-point)
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2020-06-22 22:08:58 +01:00 |
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MerryMage
|
48b2ffdde9
|
A32: Implement ASIMD VQMOVUN, VQMOVN
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2020-06-22 20:02:52 +01:00 |
|
MerryMage
|
52b8039367
|
A32: Implement VFPv5 VRINT{R,Z}
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2020-06-22 19:35:32 +01:00 |
|
MerryMage
|
47bc99ad9f
|
asimd_load_store_structures: Fix 2-byte aligned vld1.16
Previously incorrectly undefined
|
2020-06-22 18:46:22 +01:00 |
|
Lioncash
|
dd8d5497da
|
A32: Implement ASIMD VQRDMULH
|
2020-06-22 17:31:57 +01:00 |
|
Lioncash
|
0b7a111b54
|
A32: Implement ASIMD VQDMULH
|
2020-06-22 17:31:57 +01:00 |
|
Lioncash
|
39488e4aad
|
A32: Implement ASIMD VRSHRN
|
2020-06-21 23:15:43 +01:00 |
|
Lioncash
|
86b0e5c1c5
|
A32: Implement ASIMD VQSHRN
|
2020-06-21 23:15:43 +01:00 |
|
Lioncash
|
85222e3e65
|
A32: Implement ASIMD VQSHRUN
We can leverage ShiftRightNarrowing() to implement this.
|
2020-06-21 23:15:43 +01:00 |
|
MerryMage
|
562a98bcf9
|
A32: Implement ASIMD VCVT (between floating-point and fixed-point)
|
2020-06-21 20:23:40 +01:00 |
|
MerryMage
|
6f56043a73
|
A32: Implement ASIMD VFMA, VFMS
|
2020-06-21 20:21:53 +01:00 |
|
Lioncash
|
aa0358d324
|
A32: Implement ASIMD VMLAL/VMLSL (integer)
|
2020-06-21 20:03:19 +01:00 |
|
Lioncash
|
eab26b404a
|
A32: Implement ASIMD VABAL
|
2020-06-21 20:01:08 +01:00 |
|
Lioncash
|
98581839ca
|
A32: Implement ASIMD VABDL
|
2020-06-21 19:55:00 +01:00 |
|
MerryMage
|
db85e7ced5
|
asimd: Add missing three registers of different lengths instructions
|
2020-06-21 19:54:32 +01:00 |
|
Lioncash
|
95919594d1
|
A32: Implement ASIMD VQSHL/VQSHLU (immediate)
|
2020-06-21 19:26:30 +01:00 |
|
MerryMage
|
3557576ece
|
A32: Implement ASIMD AESD, AESE, AESIMC, AESMC
|
2020-06-21 18:39:57 +01:00 |
|
Fernando Sahmkow
|
2fa1c1d13c
|
A32: Allow cleaning up exclusive state from the interface.
This function is normally required for emulating certain OS mechanisms.
|
2020-06-21 18:18:33 +01:00 |
|
MerryMage
|
df58a429ee
|
A32: Implement ASIMD VQRSHRN
|
2020-06-21 17:41:18 +01:00 |
|
MerryMage
|
589d717af5
|
A32: Implement ASIMD VQRSHRUN
|
2020-06-21 17:41:18 +01:00 |
|
MerryMage
|
e009d99924
|
A32: Implement ASIMD VSHRN
|
2020-06-21 17:41:18 +01:00 |
|
MerryMage
|
473949d486
|
asimd_load_store_structures: Suppress MSVC shift warning
|
2020-06-21 17:41:18 +01:00 |
|
MerryMage
|
8f0f1cfd66
|
A32: Implement ASIMD VST{1,2,3,4} (single n-element structure from one lane)
|
2020-06-21 16:27:33 +01:00 |
|
MerryMage
|
fa145ae401
|
a32_unicorn: Print code on unicorn error
|
2020-06-21 16:23:01 +01:00 |
|
MerryMage
|
5a597f415c
|
A32: Implement A32 VLD{1,2,3,4} (single n-element structure to one lane)
|
2020-06-21 16:22:43 +01:00 |
|
MerryMage
|
f221912409
|
bit_util: Bits without template arguments
|
2020-06-21 16:07:59 +01:00 |
|
MerryMage
|
3202e4c539
|
A32: Implement ASIMD VLD{1,2,3,4} (single n-element structure to all lanes)
|
2020-06-21 15:25:26 +01:00 |
|
MerryMage
|
d7197745ac
|
emit_x64_vector_floating_point: fpcr_controlled is unused when fsize == 16 in EmitFPVectorToFixed
|
2020-06-21 14:46:06 +01:00 |
|
MerryMage
|
b32fc5ab0f
|
a64_emit_x64: EmitVAddrLookup: Use bzhi instruction when silently_mirror_page_table is active and BMI2 is available
|
2020-06-21 14:46:06 +01:00 |
|
MerryMage
|
809dfe9c54
|
A32: Implement ASIMD VCVT (between floating-point and integer)
|
2020-06-21 14:28:25 +01:00 |
|
MerryMage
|
43a4b2a0b8
|
ir_emitter: Remove dummy fpcr_controlled arguments from scalar FP instructions
|
2020-06-21 14:28:25 +01:00 |
|
MerryMage
|
c836b389c8
|
emit_x64_vector_floating_point: Add fpcr_controlled argument to all IR instructions
|
2020-06-21 14:28:25 +01:00 |
|
MerryMage
|
33a81dae68
|
asimd: VEXT was being shadowed
|
2020-06-21 13:12:19 +01:00 |
|
MerryMage
|
bf093395d8
|
A32: Implement ASIMD VMOVN
|
2020-06-21 12:35:39 +01:00 |
|
MerryMage
|
c7785cd982
|
A32: Implement ASIMD VUZP and VZIP
|
2020-06-21 12:34:55 +01:00 |
|
MerryMage
|
603cd09c8f
|
A32: Implement ASIMD VTRN
|
2020-06-21 12:14:13 +01:00 |
|
MerryMage
|
a8b481ab63
|
simd_permute: Implement TRN{1,2} in terms of VectorTranspose
|
2020-06-21 12:14:13 +01:00 |
|
MerryMage
|
7d1e103ff5
|
IR: Implement VectorTranspose
|
2020-06-21 12:14:13 +01:00 |
|
MerryMage
|
9cc11681dc
|
A32: Implement ASIMD VMLAL, VMLSL, VMULL (scalar)
|
2020-06-21 10:31:30 +01:00 |
|