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303 commits

Author SHA1 Message Date
Merry
dc37fe6e28 emit_x64_vector: Bugfix for ArithmeticShiftRightByte: shift_amount can be >= 8 2021-03-27 21:31:22 +00:00
MerryMage
f5dd7122a2 EmitFPVectorMulAdd: Correct optimization flag (Unsafe_UnfuseFMA -> Unsafe_InaccurateNaN) 2021-02-21 21:30:20 +00:00
emuplz
6d4333c78e fixed data + instruction cache callbacks (w/ tests) 2021-02-17 20:38:08 +00:00
emuplz
8728444af8 added support for instruction ic ivau 2021-02-17 20:38:06 +00:00
MerryMage
62003a2d89 A32/ir_emitter: Implement UpdateUpperLocationDescriptor 2021-02-07 20:41:48 +00:00
MerryMage
f229a68aed a32_emit_x64: Update upper_location_descriptor in BXWritePC based on final location 2021-02-07 20:41:48 +00:00
MerryMage
7e5ae6076a A32: Add arch_version option 2021-02-07 12:13:14 +00:00
bunnei
de389968eb A32: Add hook_isb option. 2021-01-28 20:47:39 -08:00
MerryMage
0f27368fda A64: Add hook_isb option 2021-01-26 23:41:21 +00:00
MerryMage
3806284cbe emit_x64{,_vector}_floating_point: Fix non-FMA execution 
Avoid repeated calls to GetArgumentInfo
 2021-01-02 20:40:32 +00:00
MerryMage
6023bcd8ad emit_x64_data_processing: Fix signed/unsigned warning 2021-01-02 20:12:48 +00:00
MerryMage
c15917b350 backend/x64: Add further Unsafe_InaccurateNaN locations 2021-01-02 20:12:48 +00:00
MerryMage
f9ccf91b94 Add Unsafe_InaccurateNaN optimization to all fma instructions 2021-01-02 17:22:50 +00:00
MerryMage
8c4463a0c1 emit_x64_data_processing: EmitSub: Use cmp where possible 2021-01-01 19:37:47 +00:00
MerryMage
e926f0b393 emit_x64_data_processing: Minor optimization for immediates in EmitSub 2021-01-01 13:35:01 +00:00
MerryMage
eeeafaf5fb Introduce Unsafe_InaccurateNaN 2021-01-01 07:18:05 +00:00
ReinUsesLisp
4a9a0d07f7 backend/{a32,a64}_emit_x64: Add config entry to mask page table pointers 
Add config entry to mask out the lower bits in page table pointers.
This is intended to allow users of Dynarmic to pack small integers
inside pointers and update the pair atomically without locks.
These lower bits can be masked out due to the expected alignment in
pointers inside the page table.

For the given usage, using AND on the pointer acts the same way as a
TEST instruction. That said when the mask value is zero, TEST is still
emitted to keep the same behavior.
 2020-12-29 19:16:46 +00:00
MerryMage
b47e5ea1e1 emit_x64_data_processing: Use BMI2 shifts where possible 2020-12-28 22:42:51 +00:00
Wunk
3e932ca55d
emit_x64_vector: Fix ArithmeticShiftRightByte zero_extend constant 
Should be shifting in _bytes_ of `0x80`. Not bits.
 2020-11-09 09:47:51 -08:00
Wunkolo
ec52922dae emit_x64_vector: Use explicit 64-bit mask constant 
Exchange `~0ull` with `0xFFFFFFFFFFFFFFFF` when generating
the `zero_extend` constant.
 2020-11-07 15:29:12 +00:00
Wunkolo
490160ef43 emit_x64_vector: GNFI implementation of ArithmeticShiftRightByte 
The bit-matrix is generated up-front and added to the constant-pool.
I'm using an embedded 64-bit broadcast here(m64bcst) which is the particular
EVEX encoded version of the instruction with AVX512VL+GNFI.

If it ever really matters, then we would ideally detect specific host
features like bare-GFNI and specific subsets of AVX512 and emit
the assembly based on that rather than by the entire Icelake uarch.
 2020-11-07 15:29:12 +00:00
Wunkolo
7df235aefb emit_x64_vector: GNFI implementation of EmitVectorLogicalShiftLeft8 
Same principle as EmitVectorLogicalShiftRight8. An 8x8 galois identity
matrix is bit-shfited to allow for arbitrary 8-bit-lane shifts.
 2020-11-07 15:29:12 +00:00
Wunkolo
5cc646ffed emit_x64_vector: GNFI implementation of EmitVectorLogicalShiftRight8 
Bitshifts of the GFNI identity matrix generates a new matrix that
applies lane-wise bitshifts as well. This allows for a fast
single-instruction implementation of a byte-lane bitshift.
 2020-11-07 15:29:12 +00:00
Wunkolo
6bb49726f4 emit_x64_vector: GNFI+SSSE3 implementation of EmitVectorReverseBits 
Performs a full 128-bit bit-reversal using only two instructions.

First by reversing all the bits of each byte using a galois matrix
multiplication(vgf2p8affineqb, Icelake), and then by reversing the bytes
themselves(pshufb, ssse3).
 2020-10-02 05:56:59 +01:00
ReinUsesLisp
eb00bea1ff backend/x64/exception_handler_posix: Fix signal stack memory leak in SigHandler 
std::malloc was being called inside SigHandler's constructor without a
std::free. This doesn't really matter as SigHandler is used as a
singleton and the OS will reclaim that memory. That said, properly
freeing memory keeps -fsanitize=address quiet.
 2020-10-02 05:56:07 +01:00
Wunkolo
c2d5f6da90 block_of_code: Add HasAVX512_Icelake 
Detect AVX512 feature support up to the [Icelake-level featureset](https://en.wikipedia.org/wiki/AVX-512#CPUs_with_AVX-512)
 2020-09-19 15:20:40 +01:00
Lioncash
889635d17d general: Resolve -Wmissing-prototypes warnings 2020-08-14 14:50:09 -04:00
Lioncash
34f4d99454 block_of_code: Remove unused variables in GenRunCode() 
These aren't used, so they can be removed.
 2020-08-14 14:35:17 -04:00
MerryMage
6bbc53839f Unsafe Optimization: Extend Unsafe_UnfuseFMA to all FMA-related instructions 2020-07-12 12:45:12 +01:00
MerryMage
d05d95c132 Improve documentation of unsafe optimizations 2020-07-12 12:41:11 +01:00
MerryMage
82417da780 emit_x64{_vector}_floating_point: Add unsafe optimizations for RSqrtEstimate and RecipEstimate 2020-07-11 14:05:57 +01:00
MerryMage
761e95eec0 A64: Add unsafe_optimizations option 
* Strength reduce FMA unsafely
 2020-07-06 21:02:30 +01:00
MerryMage
f35aaa017c IR: Add VectorDeinterleave{Even,Odd}Lower 2020-07-04 11:04:10 +01:00
MerryMage
4ba1f8b9e7 Add optimization flags to disable specific optimizations 2020-07-04 11:04:10 +01:00
MerryMage
4b8a781c04 emit_x64_floating_point: Introduce ICODE 2020-07-04 11:04:10 +01:00
MerryMage
7022281a0b emit_x64_vector_floating_point: Introduce ICODE 2020-07-04 11:04:10 +01:00
Merry
b1ff971a92 backend/x64: Temporarily avoid use of DefineValue(Argument&) 
Issues with inappropriate values in upper bits of values
 2020-06-27 10:52:59 +01:00
MerryMage
46445d0866 A64: Remove NaN accuracy setting 
Always do accuracte NaN handling.
 2020-06-24 22:26:10 +01:00
MerryMage
2008fda88b emit_x64_floating_point: Correct error in s16 rounding in EmitFPToFixed 2020-06-22 22:54:38 +01:00
MerryMage
3ea49fc6d6 A32: Implement VFPv3 VCT (between floating-point and fixed-point) 2020-06-22 22:08:58 +01:00
Fernando Sahmkow
2fa1c1d13c A32: Allow cleaning up exclusive state from the interface. 
This function is normally required for emulating certain OS mechanisms.
 2020-06-21 18:18:33 +01:00
MerryMage
d7197745ac emit_x64_vector_floating_point: fpcr_controlled is unused when fsize == 16 in EmitFPVectorToFixed 2020-06-21 14:46:06 +01:00
MerryMage
b32fc5ab0f a64_emit_x64: EmitVAddrLookup: Use bzhi instruction when silently_mirror_page_table is active and BMI2 is available 2020-06-21 14:46:06 +01:00
MerryMage
c836b389c8 emit_x64_vector_floating_point: Add fpcr_controlled argument to all IR instructions 2020-06-21 14:28:25 +01:00
MerryMage
7d1e103ff5 IR: Implement VectorTranspose 2020-06-21 12:14:13 +01:00
MerryMage
8bbc9fdbb6 A32: Implement ASIMD VTBX 2020-06-20 22:35:31 +01:00
MerryMage
92cb4a5a34 A32: Implement ASIMD VRSQRTE 2020-06-20 15:13:22 +01:00
MerryMage
6f59c2cd8e A32: Implement ASIMD VRECPE 2020-06-20 15:07:06 +01:00
MerryMage
d3dc50d718 A32: Implement ASIMD VRSQRTS 2020-06-20 15:06:06 +01:00
MerryMage
8f506c80c3 A32: Implement ASIMD VRECPS 2020-06-20 14:39:05 +01:00