MerryMage
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88e74cb2ba
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A32: Implement ASIMD VPMAX, VPMIN (integer)
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2020-07-04 11:04:10 +01:00 |
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MerryMage
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d9914b1d51
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simd_permute: Implement VectorUnzip with deinterleave lower
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2020-07-04 11:04:10 +01:00 |
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MerryMage
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f35aaa017c
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IR: Add VectorDeinterleave{Even,Odd}Lower
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2020-07-04 11:04:10 +01:00 |
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MerryMage
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df477c46c2
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asimd_load_store_structures: VST1 undef correction
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2020-07-04 11:04:10 +01:00 |
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MerryMage
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4ba1f8b9e7
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Add optimization flags to disable specific optimizations
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2020-07-04 11:04:10 +01:00 |
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MerryMage
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3eed024caf
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asimd_three_same: Ignore Q=1 for VPADD (floating-point)
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2020-07-04 11:04:10 +01:00 |
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MerryMage
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896cb46c89
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asimd_*: Standardize order of n and m to reduce confusion
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2020-07-04 11:04:10 +01:00 |
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MerryMage
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4b8a781c04
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emit_x64_floating_point: Introduce ICODE
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2020-07-04 11:04:10 +01:00 |
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MerryMage
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7022281a0b
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emit_x64_vector_floating_point: Introduce ICODE
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2020-07-04 11:04:10 +01:00 |
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Merry
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4f967387c0
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asimd_three_regs: Reimplement asimd_VMLAL in terms of WideInstruction
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2020-06-27 13:06:46 +01:00 |
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Merry
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7997404ee7
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A32: Implement ASIMD V{ADD,SUB}{W,L}
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2020-06-27 12:58:47 +01:00 |
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Merry
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868bd00ab5
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A32: Rearrange translators for ASIMD Three Registers
* Separate Three Registers with Different Lengths from Same Lengths decoders
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2020-06-27 11:15:07 +01:00 |
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Merry
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b1ff971a92
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backend/x64: Temporarily avoid use of DefineValue(Argument&)
Issues with inappropriate values in upper bits of values
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2020-06-27 10:52:59 +01:00 |
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Merry
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337498823c
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FindUnicorn: Fix find_package_handle_standard_args warning
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2020-06-27 10:06:39 +01:00 |
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MerryMage
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8a1f106dba
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decoder/asimd: Correct names of scalar exceptions
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2020-06-25 17:40:11 +01:00 |
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MerryMage
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495f58eed8
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A32: Implement ASIMD VSHLL
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2020-06-24 23:47:13 +01:00 |
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MerryMage
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ed48a9d7d5
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A32: Implement VFPv5 VRINTX
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2020-06-24 22:31:58 +01:00 |
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MerryMage
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46445d0866
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A64: Remove NaN accuracy setting
Always do accuracte NaN handling.
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2020-06-24 22:26:10 +01:00 |
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Lioncash
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b5df8d1ef8
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A32: Implement ASIMD VQDMULL (scalar)
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2020-06-23 18:19:42 +01:00 |
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Lioncash
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20a2bf29fc
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A32: Implement ASIMD VQRDMULH (scalar)
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2020-06-23 18:19:42 +01:00 |
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Lioncash
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ab5efe8632
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A32: Implement ASIMD VQDMULH (scalar)
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2020-06-23 18:19:42 +01:00 |
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MerryMage
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2008fda88b
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emit_x64_floating_point: Correct error in s16 rounding in EmitFPToFixed
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2020-06-22 22:54:38 +01:00 |
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MerryMage
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3ea49fc6d6
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A32: Implement VFPv3 VCT (between floating-point and fixed-point)
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2020-06-22 22:08:58 +01:00 |
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MerryMage
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48b2ffdde9
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A32: Implement ASIMD VQMOVUN, VQMOVN
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2020-06-22 20:02:52 +01:00 |
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MerryMage
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52b8039367
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A32: Implement VFPv5 VRINT{R,Z}
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2020-06-22 19:35:32 +01:00 |
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MerryMage
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47bc99ad9f
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asimd_load_store_structures: Fix 2-byte aligned vld1.16
Previously incorrectly undefined
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2020-06-22 18:46:22 +01:00 |
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Lioncash
|
dd8d5497da
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A32: Implement ASIMD VQRDMULH
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2020-06-22 17:31:57 +01:00 |
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Lioncash
|
0b7a111b54
|
A32: Implement ASIMD VQDMULH
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2020-06-22 17:31:57 +01:00 |
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Lioncash
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39488e4aad
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A32: Implement ASIMD VRSHRN
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2020-06-21 23:15:43 +01:00 |
|
Lioncash
|
86b0e5c1c5
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A32: Implement ASIMD VQSHRN
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2020-06-21 23:15:43 +01:00 |
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Lioncash
|
85222e3e65
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A32: Implement ASIMD VQSHRUN
We can leverage ShiftRightNarrowing() to implement this.
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2020-06-21 23:15:43 +01:00 |
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MerryMage
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562a98bcf9
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A32: Implement ASIMD VCVT (between floating-point and fixed-point)
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2020-06-21 20:23:40 +01:00 |
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MerryMage
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6f56043a73
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A32: Implement ASIMD VFMA, VFMS
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2020-06-21 20:21:53 +01:00 |
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Lioncash
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aa0358d324
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A32: Implement ASIMD VMLAL/VMLSL (integer)
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2020-06-21 20:03:19 +01:00 |
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Lioncash
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eab26b404a
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A32: Implement ASIMD VABAL
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2020-06-21 20:01:08 +01:00 |
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Lioncash
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98581839ca
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A32: Implement ASIMD VABDL
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2020-06-21 19:55:00 +01:00 |
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MerryMage
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db85e7ced5
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asimd: Add missing three registers of different lengths instructions
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2020-06-21 19:54:32 +01:00 |
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Lioncash
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95919594d1
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A32: Implement ASIMD VQSHL/VQSHLU (immediate)
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2020-06-21 19:26:30 +01:00 |
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MerryMage
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3557576ece
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A32: Implement ASIMD AESD, AESE, AESIMC, AESMC
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2020-06-21 18:39:57 +01:00 |
|
Fernando Sahmkow
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2fa1c1d13c
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A32: Allow cleaning up exclusive state from the interface.
This function is normally required for emulating certain OS mechanisms.
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2020-06-21 18:18:33 +01:00 |
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MerryMage
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df58a429ee
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A32: Implement ASIMD VQRSHRN
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2020-06-21 17:41:18 +01:00 |
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MerryMage
|
589d717af5
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A32: Implement ASIMD VQRSHRUN
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2020-06-21 17:41:18 +01:00 |
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MerryMage
|
e009d99924
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A32: Implement ASIMD VSHRN
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2020-06-21 17:41:18 +01:00 |
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MerryMage
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473949d486
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asimd_load_store_structures: Suppress MSVC shift warning
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2020-06-21 17:41:18 +01:00 |
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MerryMage
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8f0f1cfd66
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A32: Implement ASIMD VST{1,2,3,4} (single n-element structure from one lane)
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2020-06-21 16:27:33 +01:00 |
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MerryMage
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fa145ae401
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a32_unicorn: Print code on unicorn error
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2020-06-21 16:23:01 +01:00 |
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MerryMage
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5a597f415c
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A32: Implement A32 VLD{1,2,3,4} (single n-element structure to one lane)
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2020-06-21 16:22:43 +01:00 |
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MerryMage
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f221912409
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bit_util: Bits without template arguments
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2020-06-21 16:07:59 +01:00 |
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MerryMage
|
3202e4c539
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A32: Implement ASIMD VLD{1,2,3,4} (single n-element structure to all lanes)
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2020-06-21 15:25:26 +01:00 |
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MerryMage
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d7197745ac
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emit_x64_vector_floating_point: fpcr_controlled is unused when fsize == 16 in EmitFPVectorToFixed
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2020-06-21 14:46:06 +01:00 |
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