dynarmic

mirrors/dynarmic

Fork 0

Commit graph

5f7d940fde disassemble_arm: Partially implement coprocessor and hint instructions MerryMage 2016-08-18 18:21:16 +0100
36a916a766 decoder/arm: Correct NOP decoder MerryMage 2016-08-18 18:20:29 +0100
e9e7ac6e65 decoder/arm: Correct PLD decoder for v6K MerryMage 2016-08-18 18:19:34 +0100
269160ef0d emit_x64: Clear RSB-related caches when ClearCache() is called MerryMage 2016-08-18 18:18:44 +0100
1a3f3ac435 emit_x64: Correct behaviour of PackedOperation for immediate argument MerryMage 2016-08-18 18:17:17 +0100
b2de47954b EmitX64: Emit correct cycle count on cond failure MerryMage 2016-08-18 18:16:18 +0100
841098a0bc ir: separate components out a little more Lioncash 2016-08-17 10:53:36 -0400
9690d1423d intrusive_list: explicitly default relevant constructors Lioncash 2016-08-16 23:50:17 -0400
cbd99e4367 jitstate: Use std::array's fill() in ResetRSB Lioncash 2016-08-16 13:47:31 -0400
74ee92ee38 jitstate: const correctness Lioncash 2016-08-16 13:41:16 -0400
9ed9f4c565 mp: Generalize function information retrieval Lioncash 2016-08-16 12:40:04 -0400
439619c827 reg_alloc: Make GetRegLoc return by const reference Lioncash 2016-08-16 14:52:46 -0400
0ebb572e2d Optimization: Make RSB a ring buffer instead of a stack MerryMage 2016-08-15 15:48:22 +0100
7d7ac0af71 Optimization: Make SVC use RSB MerryMage 2016-08-15 15:02:08 +0100
6c45619aa1 Optimization: Implement terminal LinkBlockFast MerryMage 2016-08-15 14:33:17 +0100
624e84fa09 Optimization: Tweak RSB MerryMage 2016-08-15 14:08:06 +0100
070298b948 Optimization: bugfix! Return Stack Buffer location hash calculation was incorrect MerryMage 2016-08-15 13:21:58 +0100
e164ede4dc TranslateArm: Implement MRS, MSR (imm), MSR (reg) MerryMage 2016-08-14 19:39:16 +0100
30f3d869cc TranslateArm: Implement VPUSH and VPOP. bunnei 2016-08-13 01:51:55 -0400
9c82a12f8f ir_opt: Update VerificationPass to current IR MerryMage 2016-08-13 18:39:49 +0100
8fc21f481a RegAlloc: Handle case when def is unused MerryMage 2016-08-13 01:55:03 +0100
d43d97b990 EmitX64/EmitPushRSB: Assert that patch location is of correct size MerryMage 2016-08-13 00:52:31 +0100
960d14d18e Optimization: Implement Return Stack Buffer MerryMage 2016-08-13 00:10:23 +0100
8e68e6fdd9 TranslateArm: Implement QADD16/QSUB16/UQADD16/UQSUB16. bunnei 2016-08-12 13:42:16 -0400
4b09c0d032 TranslateArm: Implement QADD8 and UQADD8. bunnei 2016-08-12 13:26:14 -0400
127fbe99cb TranslateArm: Implement QSUB8. bunnei 2016-08-12 13:18:38 -0400
86fe29c6d2 TranslateArm: Implement UQSUB8. bunnei 2016-08-12 11:53:16 -0400
1029fd27ce Update documentation (2016-08-12) MerryMage 2016-08-12 18:17:31 +0100
3808938c98 Fix SETEND MerryMage 2016-08-11 19:15:58 +0100
218980cf69 load_store: Implement LDRSB and LDRSH. bunnei 2016-08-11 17:18:20 +0100
0e5593ba62 TranslateArm: Implement SETEND MerryMage 2016-08-11 17:15:33 +0100
8964b38cf9 IR/DumpBlock: Print references to ExtRegs MerryMage 2016-08-11 17:15:02 +0100
b4c586d5ef TranslateArm: VSTR: Correct behaviour in big-endian mode MerryMage 2016-08-10 16:43:37 +0100
945498a16a DisassemblerArm: Disassemble SETEND MerryMage 2016-08-10 16:15:07 +0100
8e8db6e137 TranslateArm: Implement VSTR. bunnei 2016-08-10 15:01:23 +0100
df39308e03 TranslateArm: Implement CLREX, LDREX, LDREXB, LDREXD, LDREXH, STREX, STREXB, STREXD, STREXH, SWP, SWPB MerryMage 2016-08-09 22:48:20 +0100
d921390928 TranslateArm: Add santity check to see if we've emitted a terminal instruction MerryMage 2016-08-09 22:47:41 +0100
2eec43178a IR: Opaque can be of any type MerryMage 2016-08-09 22:46:44 +0100
29d30bf931 Interface: Added Jit::Reset to reset CPU state MerryMage 2016-08-09 22:45:54 +0100
82f42d065f DisassemblerArm: Implemented disassembly of STR*/LDR* instructions MerryMage 2016-08-09 22:44:42 +0100
d0d51ba346 TranslateArm: Implement STM, STMDA, STMDB, STMIB MerryMage 2016-08-08 22:49:11 +0100
5d26899ac9 Add simplified LogicalShiftRight64 IR opcode Tillmann Karras 2016-08-07 14:23:33 +0100
ccb2aa96a5 Add support for the APSR.Q flag Tillmann Karras 2016-08-06 22:04:52 +0100
11e0688e5f Fix build on case-sensitive file systems Tillmann Karras 2016-08-08 10:11:54 +0100
85549d7ae2 TranslateArm: Implement LDM, LDMDA, LDMDB, LDMIB MerryMage 2016-08-08 22:21:10 +0100
46e4864707 ArmTypes: Add RegListToString and reorganise MerryMage 2016-08-08 22:20:28 +0100
975f011fc0 BackendX64/RegAlloc: Do not allocate RSP for guest use MerryMage 2016-08-08 16:01:07 +0100
abd113f160 EmitX64: Renamed patch_jmp_locations to patch_jg_locations MerryMage 2016-08-08 15:56:07 +0100
52fa998e6b EmitX64: EmitTerminalLinkBlock: Fix behaviour when setting T and E flags MerryMage 2016-08-07 22:47:43 +0100
04c1a0d2de EmitX64: Switch MXCSR when switching to interpreter MerryMage 2016-08-07 22:47:17 +0100
edb236ab07 Correct implementation of thumb16_SVC and arm_SVC MerryMage 2016-08-07 22:19:39 +0100
a32063fa60 EmitX64: Implement block linking MerryMage 2016-08-07 22:11:39 +0100
b3bb1d5048 Tests: Tidy up ARM fuzz tests MerryMage 2016-08-07 21:55:38 +0100
328422b740 RegAlloc: HostCall flushes all XMM regsiters MerryMage 2016-08-07 21:02:16 +0100
4dcd1d1859 Arm: BLX is UNPREDICTABLE when Rm is PC MerryMage 2016-08-07 20:50:33 +0100
1af5bef32c TranslateArm: Implement BLX (imm), BLX (reg) and BXJ MerryMage 2016-08-07 20:19:37 +0100
939bb5c0cb TranslateArm: Implement NOP MerryMage 2016-08-07 20:08:31 +0100
e48df9d8fd TranslateArm: Implement Hint instructions as NOPs MerryMage 2016-08-07 20:04:48 +0100
3a465ba4a8 VFP: Implement VLDR MerryMage 2016-08-07 19:59:35 +0100
a2c2db277b VFP: Implement VMOV (all variants) MerryMage 2016-08-07 19:25:12 +0100
aba705f6b9 BackendX64: Merge Routines into BlockOfCode MerryMage 2016-08-07 18:08:48 +0100
0f412247ed VFP: Implement VSQRT MerryMage 2016-08-07 12:19:07 +0100
cd8e7c0504 VFP: Implement VNEG MerryMage 2016-08-07 12:04:21 +0100
da33af5abe VFP: Implement VMLA, VMLS, VNMLA, VNMLS MerryMage 2016-08-07 11:38:30 +0100
3f1345a1a5 VFP: Implement VNMUL, VDIV MerryMage 2016-08-07 10:56:12 +0100
12e7f2c359 VFP: Implement VMUL MerryMage 2016-08-07 10:21:14 +0100
97b5fa173f VFP: Implement VSUB MerryMage 2016-08-07 01:41:25 +0100
ce6b5f8210 VFP: Implement VABS MerryMage 2016-08-07 01:27:18 +0100
f88b1b4c2e FPSCR: Save and restore MSCSR across supervisor call, fix MXCSR exception mask MerryMage 2016-08-07 00:40:29 +0100
c35f06470f VFP: Interpret VFP instructions when FPSCR.Len or FPSCR.Stride != 1 MerryMage 2016-08-06 23:01:18 +0100
94b99f5949 Common: Add an intrusive list implementation; remove use of boost::intrusive::list. MerryMage 2016-08-06 22:23:01 +0100
9264e2e04c Use XOR when loading a zero immediate Tillmann Karras 2016-08-06 21:04:13 +0100
55204a80d0 Implement SMMLA, SMMLS, SMMUL Tillmann Karras 2016-08-06 12:10:43 +0100
846d07d7b5 Add Sub64 opcode Tillmann Karras 2016-08-06 06:09:47 +0100
b9f4f1ed0f Add carry support to MostSignificantWord Tillmann Karras 2016-08-06 21:03:57 +0100
01aebcb385 Remove *MulHi wrappers Tillmann Karras 2016-08-06 05:21:29 +0100
5e047107a0 Disassemble more instructions Tillmann Karras 2016-08-06 05:18:29 +0100
f99cb613cf Disassemble packs and more multiplies Tillmann Karras 2016-08-05 02:40:44 +0100
81d9d4b012 Add Subv's sign/zero extension tests Tillmann Karras 2016-08-05 02:35:27 +0100
a281fcc744 Fix printf Tillmann Karras 2016-08-06 21:16:29 +0100
7915f97d98 TranslateArm/LoadStore: Add default case to switches for arm_LDRD_imm and arm_LDRD_reg (fixes GCC warning) MerryMage 2016-08-06 20:42:06 +0100
4d127c19dd Common: Add a memory pool implementation, remove use of boost::pool MerryMage 2016-08-06 20:41:00 +0100
411e804b0d Interface: Forward declare Arm::LocationDescriptor MerryMage 2016-08-06 19:59:09 +0100
9ab7626374 Tests/VFP: Add tests for VADD.F32 MerryMage 2016-08-06 17:31:01 +0100
4b31ea25a7 VFP: Implement VADD.{F32,F64} MerryMage 2016-08-06 17:21:29 +0100
8ff414ee0e Frontend/Decoder: 1. Remove member pointer as a template argument. 2. Sort ARM table such that unconditional instructions are on top. MerryMage 2016-08-06 17:17:58 +0100
94d5738f62 BackendX64/Routines: Add floating-point constants MerryMage 2016-08-06 17:12:40 +0100
8754728a82 BackendX64/RegAlloc: Corrected code emitted by EmitMove for XMM->Spill case MerryMage 2016-08-06 17:11:58 +0100
8cc4fe8a10 BackendX64/RegAlloc: HostLocToX64 now handles XMM registers properly MerryMage 2016-08-06 17:11:22 +0100
cd1eef2801 Merged in bunnei/dynarmic/load_store (pull request #9) Merry 2016-08-06 14:22:45 +0100
2448d52394 load_store: Use correct types for LDR/STR. bunnei 2016-08-05 20:51:32 -0400
8c2300d477 arm: Implement LDRD reg/imm instructions. bunnei 2016-08-04 23:36:58 -0400
72608b7af6 arm: Handle Cond::NV (some 3DS games use this despite being obsolete). bunnei 2016-08-04 23:14:15 -0400
ec3a98cf95 arm: Implement LDRH reg/imm instructions. bunnei 2016-08-04 23:12:45 -0400
192a0fba7a arm: Implement LDRB reg/imm instructions. bunnei 2016-08-04 23:12:11 -0400
dfb318f208 arm: Implement STRD reg/imm instructions. bunnei 2016-08-04 22:47:27 -0400
e931dc2496 arm: Implement STRH reg/imm instructions. bunnei 2016-08-04 20:47:08 -0400
9f77662b24 arm: Implement STRB reg/imm instructions. bunnei 2016-08-04 19:50:01 -0400
a5e2116e12 fuzz_arm: Log write records on failure. bunnei 2016-08-04 19:35:46 -0400
caab1bbc7c arm: Implement STR reg/imm instructions. bunnei 2016-08-04 19:35:17 -0400