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MerryMage 05e97058c3 parallel: Add and Subtract with Exchange improvements 
* Remove asx argument from PackedHalvingSubAdd{U16,S16} IR instruction
* Implement Packed{Halving,}{AddSub,SubAdd}{U16,S16} IR instructions
* Implement SASX, SSAX, UASX, USAX
2017-03-24 15:56:24 +00:00
..
arm arm/fpscr: Correct Stride implementation 2017-02-11 12:13:57 +00:00
decoder Implement CDP, LDC, MCR, MCRR, MRC, MRRC, STC 2017-01-08 14:56:06 +00:00
disassembler Implement CDP, LDC, MCR, MCRR, MRC, MRRC, STC 2017-01-08 14:56:06 +00:00
ir parallel: Add and Subtract with Exchange improvements 2017-03-24 15:56:24 +00:00
translate parallel: Add and Subtract with Exchange improvements 2017-03-24 15:56:24 +00:00