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branch.cpp
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Implement DC instructions
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2020-04-22 20:46:14 +01:00 |
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data_processing_addsub.cpp
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General: Convert multiple namespace specifiers to nested namespace specifiers where applicable
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2020-04-22 20:44:38 +01:00 |
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data_processing_bitfield.cpp
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A64: Implement EXTR
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2020-04-22 20:46:12 +01:00 |
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data_processing_conditional_compare.cpp
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A64: Implement CCMP (immediate)
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2020-04-22 20:46:13 +01:00 |
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data_processing_conditional_select.cpp
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General: Convert multiple namespace specifiers to nested namespace specifiers where applicable
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2020-04-22 20:44:38 +01:00 |
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data_processing_crc32.cpp
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A64: Implement CRC32
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2020-04-22 20:46:12 +01:00 |
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data_processing_logical.cpp
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General: Convert multiple namespace specifiers to nested namespace specifiers where applicable
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2020-04-22 20:44:38 +01:00 |
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data_processing_multiply.cpp
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A64: Move SDIV and UDIV out of data_processing_multiply.cpp
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2020-04-22 20:46:13 +01:00 |
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data_processing_pcrel.cpp
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General: Convert multiple namespace specifiers to nested namespace specifiers where applicable
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2020-04-22 20:44:38 +01:00 |
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data_processing_register.cpp
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A64: Move SDIV and UDIV out of data_processing_multiply.cpp
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2020-04-22 20:46:13 +01:00 |
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data_processing_shift.cpp
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General: Convert multiple namespace specifiers to nested namespace specifiers where applicable
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2020-04-22 20:44:38 +01:00 |
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exception_generating.cpp
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Implement DC instructions
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2020-04-22 20:46:14 +01:00 |
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floating_point_compare.cpp
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IR: FPCompare{32,64} now return NZCV flags instead of implicitly setting them
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2020-04-22 20:46:13 +01:00 |
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floating_point_conditional_compare.cpp
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A64: Implement FCCMPE
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2020-04-22 20:46:13 +01:00 |
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floating_point_conditional_select.cpp
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A64: Implement FCSEL
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2020-04-22 20:46:13 +01:00 |
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floating_point_conversion_fixed_point.cpp
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IR: Initial implementation of FP{Double,Single}ToFixed{S,U}{32,64}
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2020-04-22 20:46:19 +01:00 |
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floating_point_conversion_integer.cpp
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A64: Implement FCVTMU (scalar)
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2020-04-22 20:46:19 +01:00 |
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floating_point_data_processing_one_register.cpp
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A64: Implement FRINTX, FRINTI (scalar)
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2020-04-22 20:46:20 +01:00 |
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floating_point_data_processing_three_register.cpp
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A64: Implement FNMSUB
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2020-04-22 20:46:18 +01:00 |
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floating_point_data_processing_two_register.cpp
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A64: Implement FMINNM (scalar)
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2020-04-22 20:46:15 +01:00 |
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impl.cpp
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translate: zero extend result in Vpart when storing to lower part of vector
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2020-04-22 20:46:17 +01:00 |
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impl.h
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A64: Implement UQXTN (vector)
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2020-04-22 20:46:22 +01:00 |
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load_store_exclusive.cpp
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Exclusive fixups
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2020-04-22 20:46:14 +01:00 |
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load_store_load_literal.cpp
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A64: Implement LDR (literal, SIMD&FP)
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2020-04-22 20:46:18 +01:00 |
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load_store_multiple_structures.cpp
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load_store_multiple_structures: Improve IR codegen for selem == 1 case
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2020-04-22 20:46:14 +01:00 |
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load_store_register_immediate.cpp
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A64: Add missing decoding for PRFM (unscaled offset)
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2020-04-22 20:46:17 +01:00 |
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load_store_register_pair.cpp
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A64: Implement LDP (SIMD&FP) and STP (SIMD&FP)
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2020-04-22 20:44:38 +01:00 |
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load_store_register_register_offset.cpp
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A64: Implement STR (register, SIMD&FP), LDR (register, SIMD&FP)
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2020-04-22 20:46:14 +01:00 |
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load_store_register_unprivileged.cpp
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General: Convert multiple namespace specifiers to nested namespace specifiers where applicable
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2020-04-22 20:44:38 +01:00 |
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load_store_single_structure.cpp
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A64: Implement load/store single structure instructions
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2020-04-22 20:46:18 +01:00 |
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move_wide.cpp
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General: Convert multiple namespace specifiers to nested namespace specifiers where applicable
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2020-04-22 20:44:38 +01:00 |
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simd_across_lanes.cpp
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A64: Implement FMAXV, FMINV, FMAXNMV, and FMINNMV
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2020-04-22 20:46:21 +01:00 |
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simd_aes.cpp
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A64: Implement AESD
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2020-04-22 20:46:13 +01:00 |
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simd_copy.cpp
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A64: Implement DUP (element), scalar variant
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2020-04-22 20:46:14 +01:00 |
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simd_crypto_four_register.cpp
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A64: Implement SM3SS1
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2020-04-22 20:46:16 +01:00 |
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simd_crypto_three_register.cpp
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translate: Return by bool in helpers where applicable
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2020-04-22 20:46:21 +01:00 |
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simd_extract.cpp
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A64: Implement EXT
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2020-04-22 20:46:19 +01:00 |
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simd_modified_immediate.cpp
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A64: Implement FMOV (vector, immediate) and mark other SIMD modified immediate instructions as unallocated
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2020-04-22 20:46:15 +01:00 |
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simd_permute.cpp
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translate: Return by bool in helpers where applicable
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2020-04-22 20:46:21 +01:00 |
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simd_scalar_pairwise.cpp
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A64: Implement FMAXP, FMINP, FMAXNMP and FMINNMP's scalar double/single-precision variant
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2020-04-22 20:46:21 +01:00 |
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simd_scalar_shift_by_immediate.cpp
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translate: Return by bool in helpers where applicable
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2020-04-22 20:46:21 +01:00 |
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simd_scalar_three_same.cpp
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A64: Implement FRSQRTS (scalar), single/double variant
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2020-04-22 20:46:22 +01:00 |
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simd_scalar_two_register_misc.cpp
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simd_scalar_two_register_misc: Implement FRSQRTE, scalar variant
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2020-04-22 20:46:21 +01:00 |
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simd_scalar_x_indexed_element.cpp
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A64: Implement FMLA and FMLS (by element)'s double/single-precision scalar variant
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2020-04-22 20:46:21 +01:00 |
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simd_sha.cpp
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A64: Implement SHA256H and SHA256H2
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2020-04-22 20:46:16 +01:00 |
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simd_sha512.cpp
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A64: Implement SM4EKEY
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2020-04-22 20:46:17 +01:00 |
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simd_shift_by_immediate.cpp
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A64: Implement SQSHRUN, SQRSHRUN (vector)
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2020-04-22 20:46:22 +01:00 |
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simd_three_different.cpp
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simd_three_different: Deduplicate common implementations
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2020-04-22 20:46:19 +01:00 |
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simd_three_same.cpp
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A64: Implement FRSQRTS (vector), single/double variant
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2020-04-22 20:46:22 +01:00 |
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simd_two_register_misc.cpp
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A64: Implement UQXTN (vector)
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2020-04-22 20:46:22 +01:00 |
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simd_vector_x_indexed_element.cpp
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translate: Return by bool in helpers where applicable
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2020-04-22 20:46:21 +01:00 |
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sys_dc.cpp
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Correct typo in DataCacheOperation enum
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2020-04-22 20:46:18 +01:00 |
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system.cpp
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a64_emit_x64: Ensure host has updated ticks in EmitA64GetCNTPCT
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2020-04-22 20:46:21 +01:00 |
