2018-01-06 21:15:25 +00:00
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/* This file is part of the dynarmic project.
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* Copyright (c) 2016 MerryMage
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* This software may be used and distributed according to the terms of the GNU
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* General Public License version 2 or any later version.
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*/
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2018-02-12 19:49:56 +00:00
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#include <initializer_list>
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2018-06-05 12:27:37 +01:00
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#include <dynarmic/A64/exclusive_monitor.h>
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2018-01-27 23:42:30 +00:00
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#include <fmt/ostream.h>
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2018-01-06 21:15:25 +00:00
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#include "backend_x64/a64_emit_x64.h"
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#include "backend_x64/a64_jitstate.h"
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#include "backend_x64/abi.h"
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#include "backend_x64/block_of_code.h"
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2018-01-08 18:33:42 +00:00
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#include "backend_x64/devirtualize.h"
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2018-01-06 21:15:25 +00:00
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#include "backend_x64/emit_x64.h"
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#include "common/address_range.h"
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#include "common/assert.h"
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#include "common/bit_util.h"
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#include "common/common_types.h"
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#include "common/variant_util.h"
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#include "frontend/A64/location_descriptor.h"
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#include "frontend/A64/types.h"
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#include "frontend/ir/basic_block.h"
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#include "frontend/ir/microinstruction.h"
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#include "frontend/ir/opcodes.h"
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// TODO: Have ARM flags in host flags and not have them use up GPR registers unless necessary.
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// TODO: Actually implement that proper instruction selector you've always wanted to sweetheart.
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2018-01-26 13:51:48 +00:00
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namespace Dynarmic::BackendX64 {
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2018-01-06 21:15:25 +00:00
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using namespace Xbyak::util;
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2018-02-18 13:00:41 +00:00
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A64EmitContext::A64EmitContext(const A64::UserConfig& conf, RegAlloc& reg_alloc, IR::Block& block)
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: EmitContext(reg_alloc, block), conf(conf) {}
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2018-01-06 21:15:25 +00:00
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A64::LocationDescriptor A64EmitContext::Location() const {
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return A64::LocationDescriptor{block.Location()};
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}
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2018-07-14 07:08:15 +01:00
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FP::RoundingMode A64EmitContext::FPSCR_RMode() const {
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return Location().FPCR().RMode();
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}
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2018-01-06 21:15:25 +00:00
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bool A64EmitContext::FPSCR_RoundTowardsZero() const {
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2018-06-26 15:10:44 +01:00
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return Location().FPCR().RMode() != FP::RoundingMode::TowardsZero;
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2018-01-06 21:15:25 +00:00
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}
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bool A64EmitContext::FPSCR_FTZ() const {
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return Location().FPCR().FZ();
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}
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bool A64EmitContext::FPSCR_DN() const {
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2018-02-18 13:04:45 +00:00
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return Location().FPCR().DN() || conf.floating_point_nan_accuracy == A64::UserConfig::NaNAccuracy::AlwaysForceDefaultNaN;
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}
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bool A64EmitContext::AccurateNaN() const {
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return conf.floating_point_nan_accuracy == A64::UserConfig::NaNAccuracy::Accurate;
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2018-01-06 21:15:25 +00:00
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}
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2018-02-03 14:28:57 +00:00
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A64EmitX64::A64EmitX64(BlockOfCode& code, A64::UserConfig conf)
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2018-01-06 21:15:25 +00:00
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: EmitX64(code), conf(conf)
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{
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2018-02-12 18:18:47 +00:00
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GenMemory128Accessors();
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2018-02-12 19:49:56 +00:00
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GenFastmemFallbacks();
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2018-02-03 14:28:57 +00:00
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code.PreludeComplete();
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2018-01-06 21:15:25 +00:00
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}
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2018-01-24 02:11:07 +00:00
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A64EmitX64::~A64EmitX64() = default;
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2018-01-06 21:15:25 +00:00
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A64EmitX64::BlockDescriptor A64EmitX64::Emit(IR::Block& block) {
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2018-02-03 14:28:57 +00:00
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code.align();
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const u8* const entrypoint = code.getCurr();
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2018-01-06 21:15:25 +00:00
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// Start emitting.
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EmitCondPrelude(block);
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RegAlloc reg_alloc{code, A64JitState::SpillCount, SpillToOpArg<A64JitState>};
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2018-02-18 13:00:41 +00:00
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A64EmitContext ctx{conf, reg_alloc, block};
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2018-01-06 21:15:25 +00:00
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for (auto iter = block.begin(); iter != block.end(); ++iter) {
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IR::Inst* inst = &*iter;
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// Call the relevant Emit* member function.
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switch (inst->GetOpcode()) {
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#define OPCODE(name, type, ...) \
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case IR::Opcode::name: \
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A64EmitX64::Emit##name(ctx, inst); \
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break;
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#define A32OPC(...)
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#define A64OPC(name, type, ...) \
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case IR::Opcode::A64##name: \
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A64EmitX64::EmitA64##name(ctx, inst); \
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break;
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#include "frontend/ir/opcodes.inc"
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#undef OPCODE
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#undef A32OPC
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#undef A64OPC
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default:
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2018-01-27 23:42:30 +00:00
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ASSERT_MSG(false, "Invalid opcode: {}", inst->GetOpcode());
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2018-01-06 21:15:25 +00:00
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break;
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}
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2018-01-10 02:05:08 +00:00
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ctx.reg_alloc.EndOfAllocScope();
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2018-01-06 21:15:25 +00:00
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}
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reg_alloc.AssertNoMoreUses();
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EmitAddCycles(block.CycleCount());
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EmitX64::EmitTerminal(block.GetTerminal(), block.Location());
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2018-02-03 14:28:57 +00:00
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code.int3();
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2018-01-06 21:15:25 +00:00
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const A64::LocationDescriptor descriptor{block.Location()};
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Patch(descriptor, entrypoint);
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2018-02-03 14:28:57 +00:00
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const size_t size = static_cast<size_t>(code.getCurr() - entrypoint);
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2018-01-06 21:15:25 +00:00
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const A64::LocationDescriptor end_location{block.EndLocation()};
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const auto range = boost::icl::discrete_interval<u64>::closed(descriptor.PC(), end_location.PC() - 1);
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2018-01-23 19:16:39 +00:00
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A64EmitX64::BlockDescriptor block_desc{entrypoint, size};
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2018-01-06 21:15:25 +00:00
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block_descriptors.emplace(descriptor.UniqueHash(), block_desc);
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2018-01-23 19:16:39 +00:00
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block_ranges.AddRange(range, descriptor);
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2018-01-06 21:15:25 +00:00
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return block_desc;
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}
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2018-01-23 19:16:39 +00:00
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void A64EmitX64::ClearCache() {
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EmitX64::ClearCache();
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block_ranges.ClearCache();
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}
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void A64EmitX64::InvalidateCacheRanges(const boost::icl::interval_set<u64>& ranges) {
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InvalidateBasicBlocks(block_ranges.InvalidateRanges(ranges));
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}
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2018-02-12 18:18:47 +00:00
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void A64EmitX64::GenMemory128Accessors() {
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code.align();
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memory_read_128 = code.getCurr<void(*)()>();
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#ifdef _WIN32
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DEVIRT(conf.callbacks, &A64::UserCallbacks::MemoryRead128).EmitCallWithReturnPointer(code, [&](Xbyak::Reg64 return_value_ptr, RegList args) {
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code.mov(code.ABI_PARAM3, code.ABI_PARAM2);
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code.sub(rsp, 8 + 16 + ABI_SHADOW_SPACE);
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code.lea(return_value_ptr, ptr[rsp + ABI_SHADOW_SPACE]);
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});
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code.movups(xmm0, xword[code.ABI_RETURN]);
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code.add(rsp, 8 + 16 + ABI_SHADOW_SPACE);
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#else
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code.sub(rsp, 8);
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DEVIRT(conf.callbacks, &A64::UserCallbacks::MemoryRead128).EmitCall(code);
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
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code.movq(xmm0, code.ABI_RETURN);
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code.pinsrq(xmm0, code.ABI_RETURN2, 1);
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} else {
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code.movq(xmm0, code.ABI_RETURN);
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code.movq(xmm1, code.ABI_RETURN2);
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code.punpcklqdq(xmm0, xmm1);
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}
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code.add(rsp, 8);
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#endif
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code.ret();
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code.align();
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memory_write_128 = code.getCurr<void(*)()>();
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#ifdef _WIN32
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code.sub(rsp, 8 + 16 + ABI_SHADOW_SPACE);
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code.lea(code.ABI_PARAM3, ptr[rsp + ABI_SHADOW_SPACE]);
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code.movaps(xword[code.ABI_PARAM3], xmm0);
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DEVIRT(conf.callbacks, &A64::UserCallbacks::MemoryWrite128).EmitCall(code);
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code.add(rsp, 8 + 16 + ABI_SHADOW_SPACE);
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#else
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code.sub(rsp, 8);
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
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code.movq(code.ABI_PARAM3, xmm0);
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code.pextrq(code.ABI_PARAM4, xmm0, 1);
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} else {
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code.movq(code.ABI_PARAM3, xmm0);
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code.punpckhqdq(xmm0, xmm0);
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code.movq(code.ABI_PARAM4, xmm0);
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}
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DEVIRT(conf.callbacks, &A64::UserCallbacks::MemoryWrite128).EmitCall(code);
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code.add(rsp, 8);
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#endif
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code.ret();
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}
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2018-02-12 19:49:56 +00:00
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void A64EmitX64::GenFastmemFallbacks() {
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const std::initializer_list<int> idxes{0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15};
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const std::vector<std::tuple<size_t, ArgCallback>> read_callbacks {
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{8, DEVIRT(conf.callbacks, &A64::UserCallbacks::MemoryRead8)},
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{16, DEVIRT(conf.callbacks, &A64::UserCallbacks::MemoryRead16)},
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{32, DEVIRT(conf.callbacks, &A64::UserCallbacks::MemoryRead32)},
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{64, DEVIRT(conf.callbacks, &A64::UserCallbacks::MemoryRead64)},
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};
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const std::vector<std::tuple<size_t, ArgCallback>> write_callbacks {
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{8, DEVIRT(conf.callbacks, &A64::UserCallbacks::MemoryWrite8)},
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{16, DEVIRT(conf.callbacks, &A64::UserCallbacks::MemoryWrite16)},
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{32, DEVIRT(conf.callbacks, &A64::UserCallbacks::MemoryWrite32)},
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{64, DEVIRT(conf.callbacks, &A64::UserCallbacks::MemoryWrite64)},
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};
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for (int vaddr_idx : idxes) {
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if (vaddr_idx == 4 || vaddr_idx == 15) {
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continue;
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}
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for (int value_idx : idxes) {
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code.align();
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read_fallbacks[std::make_tuple(128, vaddr_idx, value_idx)] = code.getCurr<void(*)()>();
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ABI_PushCallerSaveRegistersAndAdjustStackExcept(code, HostLocXmmIdx(value_idx));
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if (vaddr_idx != code.ABI_PARAM2.getIdx()) {
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code.mov(code.ABI_PARAM2, Xbyak::Reg64{vaddr_idx});
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}
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code.call(memory_read_128);
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if (value_idx != 0) {
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code.movaps(Xbyak::Xmm{value_idx}, xmm0);
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}
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ABI_PopCallerSaveRegistersAndAdjustStackExcept(code, HostLocXmmIdx(value_idx));
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code.ret();
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code.align();
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write_fallbacks[std::make_tuple(128, vaddr_idx, value_idx)] = code.getCurr<void(*)()>();
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ABI_PushCallerSaveRegistersAndAdjustStack(code);
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if (vaddr_idx != code.ABI_PARAM2.getIdx()) {
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code.mov(code.ABI_PARAM2, Xbyak::Reg64{vaddr_idx});
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}
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if (value_idx != 0) {
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code.movaps(xmm0, Xbyak::Xmm{value_idx});
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}
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code.call(memory_write_128);
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ABI_PopCallerSaveRegistersAndAdjustStack(code);
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code.ret();
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A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR
2018-02-13 00:19:04 +00:00
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if (value_idx == 4 || value_idx == 15) {
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2018-02-12 19:49:56 +00:00
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continue;
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}
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for (auto& [bitsize, callback] : read_callbacks) {
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code.align();
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read_fallbacks[std::make_tuple(bitsize, vaddr_idx, value_idx)] = code.getCurr<void(*)()>();
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ABI_PushCallerSaveRegistersAndAdjustStackExcept(code, HostLocRegIdx(value_idx));
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if (vaddr_idx != code.ABI_PARAM2.getIdx()) {
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code.mov(code.ABI_PARAM2, Xbyak::Reg64{vaddr_idx});
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}
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callback.EmitCall(code);
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if (value_idx != code.ABI_RETURN.getIdx()) {
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code.mov(Xbyak::Reg64{value_idx}, code.ABI_RETURN);
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}
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ABI_PopCallerSaveRegistersAndAdjustStackExcept(code, HostLocRegIdx(value_idx));
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code.ret();
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}
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for (auto& [bitsize, callback] : write_callbacks) {
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code.align();
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write_fallbacks[std::make_tuple(bitsize, vaddr_idx, value_idx)] = code.getCurr<void(*)()>();
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ABI_PushCallerSaveRegistersAndAdjustStack(code);
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if (vaddr_idx == code.ABI_PARAM3.getIdx() && value_idx == code.ABI_PARAM2.getIdx()) {
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code.xchg(code.ABI_PARAM2, code.ABI_PARAM3);
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A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR
2018-02-13 00:19:04 +00:00
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} else if (vaddr_idx == code.ABI_PARAM3.getIdx()) {
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code.mov(code.ABI_PARAM2, Xbyak::Reg64{vaddr_idx});
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if (value_idx != code.ABI_PARAM3.getIdx()) {
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code.mov(code.ABI_PARAM3, Xbyak::Reg64{value_idx});
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2018-02-12 19:49:56 +00:00
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}
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A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR
2018-02-13 00:19:04 +00:00
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} else {
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2018-02-12 19:49:56 +00:00
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if (value_idx != code.ABI_PARAM3.getIdx()) {
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code.mov(code.ABI_PARAM3, Xbyak::Reg64{value_idx});
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}
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A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR
2018-02-13 00:19:04 +00:00
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if (vaddr_idx != code.ABI_PARAM2.getIdx()) {
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code.mov(code.ABI_PARAM2, Xbyak::Reg64{vaddr_idx});
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}
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2018-02-12 19:49:56 +00:00
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}
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callback.EmitCall(code);
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ABI_PopCallerSaveRegistersAndAdjustStack(code);
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code.ret();
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}
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}
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}
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}
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2018-01-07 16:33:02 +00:00
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void A64EmitX64::EmitA64SetCheckBit(A64EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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Xbyak::Reg8 to_store = ctx.reg_alloc.UseGpr(args[0]).cvt8();
|
2018-02-03 14:28:57 +00:00
|
|
|
code.mov(code.byte[r15 + offsetof(A64JitState, check_bit)], to_store);
|
2018-01-07 16:33:02 +00:00
|
|
|
}
|
|
|
|
|
2018-01-07 11:31:20 +00:00
|
|
|
void A64EmitX64::EmitA64GetCFlag(A64EmitContext& ctx, IR::Inst* inst) {
|
|
|
|
Xbyak::Reg32 result = ctx.reg_alloc.ScratchGpr().cvt32();
|
2018-02-03 14:28:57 +00:00
|
|
|
code.mov(result, dword[r15 + offsetof(A64JitState, CPSR_nzcv)]);
|
|
|
|
code.shr(result, 29);
|
|
|
|
code.and_(result, 1);
|
2018-01-07 11:31:20 +00:00
|
|
|
ctx.reg_alloc.DefineValue(inst, result);
|
|
|
|
}
|
|
|
|
|
|
|
|
void A64EmitX64::EmitA64SetNZCV(A64EmitContext& ctx, IR::Inst* inst) {
|
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
2018-01-09 21:20:55 +00:00
|
|
|
Xbyak::Reg32 to_store = ctx.reg_alloc.UseScratchGpr(args[0]).cvt32();
|
2018-02-03 14:28:57 +00:00
|
|
|
code.and_(to_store, 0b11000001'00000001);
|
|
|
|
code.imul(to_store, to_store, 0b00010000'00100001);
|
|
|
|
code.shl(to_store, 16);
|
|
|
|
code.and_(to_store, 0xF0000000);
|
|
|
|
code.mov(dword[r15 + offsetof(A64JitState, CPSR_nzcv)], to_store);
|
2018-01-07 11:31:20 +00:00
|
|
|
}
|
|
|
|
|
2018-01-07 00:11:57 +00:00
|
|
|
void A64EmitX64::EmitA64GetW(A64EmitContext& ctx, IR::Inst* inst) {
|
|
|
|
A64::Reg reg = inst->GetArg(0).GetA64RegRef();
|
|
|
|
|
|
|
|
Xbyak::Reg32 result = ctx.reg_alloc.ScratchGpr().cvt32();
|
2018-02-03 14:28:57 +00:00
|
|
|
code.mov(result, dword[r15 + offsetof(A64JitState, reg) + sizeof(u64) * static_cast<size_t>(reg)]);
|
2018-01-07 00:11:57 +00:00
|
|
|
ctx.reg_alloc.DefineValue(inst, result);
|
|
|
|
}
|
|
|
|
|
|
|
|
void A64EmitX64::EmitA64GetX(A64EmitContext& ctx, IR::Inst* inst) {
|
|
|
|
A64::Reg reg = inst->GetArg(0).GetA64RegRef();
|
|
|
|
|
|
|
|
Xbyak::Reg64 result = ctx.reg_alloc.ScratchGpr();
|
2018-02-03 14:28:57 +00:00
|
|
|
code.mov(result, qword[r15 + offsetof(A64JitState, reg) + sizeof(u64) * static_cast<size_t>(reg)]);
|
2018-01-07 00:11:57 +00:00
|
|
|
ctx.reg_alloc.DefineValue(inst, result);
|
|
|
|
}
|
|
|
|
|
2018-01-26 18:35:19 +00:00
|
|
|
void A64EmitX64::EmitA64GetS(A64EmitContext& ctx, IR::Inst* inst) {
|
|
|
|
A64::Vec vec = inst->GetArg(0).GetA64VecRef();
|
|
|
|
auto addr = qword[r15 + offsetof(A64JitState, vec) + sizeof(u64) * 2 * static_cast<size_t>(vec)];
|
|
|
|
|
|
|
|
Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm();
|
2018-02-03 14:28:57 +00:00
|
|
|
code.movd(result, addr);
|
2018-01-26 18:35:19 +00:00
|
|
|
ctx.reg_alloc.DefineValue(inst, result);
|
|
|
|
}
|
|
|
|
|
2018-01-21 17:45:43 +00:00
|
|
|
void A64EmitX64::EmitA64GetD(A64EmitContext& ctx, IR::Inst* inst) {
|
|
|
|
A64::Vec vec = inst->GetArg(0).GetA64VecRef();
|
|
|
|
auto addr = qword[r15 + offsetof(A64JitState, vec) + sizeof(u64) * 2 * static_cast<size_t>(vec)];
|
|
|
|
|
|
|
|
Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm();
|
2018-02-03 14:28:57 +00:00
|
|
|
code.movq(result, addr);
|
2018-01-21 17:45:43 +00:00
|
|
|
ctx.reg_alloc.DefineValue(inst, result);
|
|
|
|
}
|
|
|
|
|
|
|
|
void A64EmitX64::EmitA64GetQ(A64EmitContext& ctx, IR::Inst* inst) {
|
|
|
|
A64::Vec vec = inst->GetArg(0).GetA64VecRef();
|
2018-01-26 18:34:22 +00:00
|
|
|
auto addr = xword[r15 + offsetof(A64JitState, vec) + sizeof(u64) * 2 * static_cast<size_t>(vec)];
|
2018-01-21 17:45:43 +00:00
|
|
|
|
|
|
|
Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm();
|
2018-02-03 14:28:57 +00:00
|
|
|
code.movaps(result, addr);
|
2018-01-21 17:45:43 +00:00
|
|
|
ctx.reg_alloc.DefineValue(inst, result);
|
|
|
|
}
|
|
|
|
|
2018-01-07 11:31:20 +00:00
|
|
|
void A64EmitX64::EmitA64GetSP(A64EmitContext& ctx, IR::Inst* inst) {
|
|
|
|
Xbyak::Reg64 result = ctx.reg_alloc.ScratchGpr();
|
2018-02-03 14:28:57 +00:00
|
|
|
code.mov(result, qword[r15 + offsetof(A64JitState, sp)]);
|
2018-01-07 11:31:20 +00:00
|
|
|
ctx.reg_alloc.DefineValue(inst, result);
|
|
|
|
}
|
|
|
|
|
2018-02-20 17:38:29 +00:00
|
|
|
void A64EmitX64::EmitA64GetFPCR(A64EmitContext& ctx, IR::Inst* inst) {
|
2018-02-20 20:29:15 +00:00
|
|
|
Xbyak::Reg32 result = ctx.reg_alloc.ScratchGpr().cvt32();
|
|
|
|
code.mov(result, dword[r15 + offsetof(A64JitState, fpcr)]);
|
2018-02-20 17:38:29 +00:00
|
|
|
ctx.reg_alloc.DefineValue(inst, result);
|
|
|
|
}
|
|
|
|
|
|
|
|
static u32 GetFPSRImpl(A64JitState* jit_state) {
|
|
|
|
return jit_state->GetFpsr();
|
|
|
|
}
|
|
|
|
|
|
|
|
void A64EmitX64::EmitA64GetFPSR(A64EmitContext& ctx, IR::Inst* inst) {
|
|
|
|
ctx.reg_alloc.HostCall(inst);
|
|
|
|
code.mov(code.ABI_PARAM1, code.r15);
|
|
|
|
code.stmxcsr(code.dword[code.r15 + offsetof(A64JitState, guest_MXCSR)]);
|
|
|
|
code.CallFunction(GetFPSRImpl);
|
|
|
|
}
|
|
|
|
|
2018-01-07 00:11:57 +00:00
|
|
|
void A64EmitX64::EmitA64SetW(A64EmitContext& ctx, IR::Inst* inst) {
|
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
|
|
A64::Reg reg = inst->GetArg(0).GetA64RegRef();
|
2018-01-09 21:21:15 +00:00
|
|
|
auto addr = qword[r15 + offsetof(A64JitState, reg) + sizeof(u64) * static_cast<size_t>(reg)];
|
2018-01-15 21:47:28 +00:00
|
|
|
if (args[1].FitsInImmediateS32()) {
|
2018-02-03 14:28:57 +00:00
|
|
|
code.mov(addr, args[1].GetImmediateS32());
|
2018-01-07 00:11:57 +00:00
|
|
|
} else {
|
2018-01-09 21:21:15 +00:00
|
|
|
// TODO: zext tracking, xmm variant
|
|
|
|
Xbyak::Reg64 to_store = ctx.reg_alloc.UseScratchGpr(args[1]);
|
2018-02-03 14:28:57 +00:00
|
|
|
code.mov(to_store.cvt32(), to_store.cvt32());
|
|
|
|
code.mov(addr, to_store);
|
2018-01-07 00:11:57 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void A64EmitX64::EmitA64SetX(A64EmitContext& ctx, IR::Inst* inst) {
|
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
|
|
A64::Reg reg = inst->GetArg(0).GetA64RegRef();
|
|
|
|
auto addr = qword[r15 + offsetof(A64JitState, reg) + sizeof(u64) * static_cast<size_t>(reg)];
|
2018-01-13 17:59:50 +00:00
|
|
|
if (args[1].FitsInImmediateS32()) {
|
2018-02-03 14:28:57 +00:00
|
|
|
code.mov(addr, args[1].GetImmediateS32());
|
2018-01-07 00:11:57 +00:00
|
|
|
} else if (args[1].IsInXmm()) {
|
|
|
|
Xbyak::Xmm to_store = ctx.reg_alloc.UseXmm(args[1]);
|
2018-02-03 14:28:57 +00:00
|
|
|
code.movq(addr, to_store);
|
2018-01-07 00:11:57 +00:00
|
|
|
} else {
|
|
|
|
Xbyak::Reg64 to_store = ctx.reg_alloc.UseGpr(args[1]);
|
2018-02-03 14:28:57 +00:00
|
|
|
code.mov(addr, to_store);
|
2018-01-07 00:11:57 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-01-26 18:34:22 +00:00
|
|
|
void A64EmitX64::EmitA64SetS(A64EmitContext& ctx, IR::Inst* inst) {
|
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
|
|
A64::Vec vec = inst->GetArg(0).GetA64VecRef();
|
|
|
|
auto addr = xword[r15 + offsetof(A64JitState, vec) + sizeof(u64) * 2 * static_cast<size_t>(vec)];
|
|
|
|
|
|
|
|
Xbyak::Xmm to_store = ctx.reg_alloc.UseXmm(args[1]);
|
|
|
|
Xbyak::Xmm tmp = ctx.reg_alloc.ScratchXmm();
|
|
|
|
// TODO: Optimize
|
2018-02-03 14:28:57 +00:00
|
|
|
code.pxor(tmp, tmp);
|
|
|
|
code.movss(tmp, to_store);
|
|
|
|
code.movaps(addr, tmp);
|
2018-01-26 18:34:22 +00:00
|
|
|
}
|
|
|
|
|
2018-01-21 17:45:43 +00:00
|
|
|
void A64EmitX64::EmitA64SetD(A64EmitContext& ctx, IR::Inst* inst) {
|
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
|
|
A64::Vec vec = inst->GetArg(0).GetA64VecRef();
|
2018-01-26 18:34:22 +00:00
|
|
|
auto addr = xword[r15 + offsetof(A64JitState, vec) + sizeof(u64) * 2 * static_cast<size_t>(vec)];
|
2018-01-21 17:45:43 +00:00
|
|
|
|
|
|
|
Xbyak::Xmm to_store = ctx.reg_alloc.UseScratchXmm(args[1]);
|
2018-02-03 14:28:57 +00:00
|
|
|
code.movq(to_store, to_store); // TODO: Remove when able
|
|
|
|
code.movaps(addr, to_store);
|
2018-01-21 17:45:43 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void A64EmitX64::EmitA64SetQ(A64EmitContext& ctx, IR::Inst* inst) {
|
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
|
|
A64::Vec vec = inst->GetArg(0).GetA64VecRef();
|
2018-01-26 18:34:22 +00:00
|
|
|
auto addr = xword[r15 + offsetof(A64JitState, vec) + sizeof(u64) * 2 * static_cast<size_t>(vec)];
|
2018-01-21 17:45:43 +00:00
|
|
|
|
|
|
|
Xbyak::Xmm to_store = ctx.reg_alloc.UseXmm(args[1]);
|
2018-02-03 14:28:57 +00:00
|
|
|
code.movaps(addr, to_store);
|
2018-01-21 17:45:43 +00:00
|
|
|
}
|
|
|
|
|
2018-01-07 11:31:20 +00:00
|
|
|
void A64EmitX64::EmitA64SetSP(A64EmitContext& ctx, IR::Inst* inst) {
|
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
|
|
auto addr = qword[r15 + offsetof(A64JitState, sp)];
|
2018-01-27 00:38:09 +00:00
|
|
|
if (args[0].FitsInImmediateS32()) {
|
2018-02-03 14:28:57 +00:00
|
|
|
code.mov(addr, args[0].GetImmediateS32());
|
2018-01-07 11:31:20 +00:00
|
|
|
} else if (args[0].IsInXmm()) {
|
|
|
|
Xbyak::Xmm to_store = ctx.reg_alloc.UseXmm(args[0]);
|
2018-02-03 14:28:57 +00:00
|
|
|
code.movq(addr, to_store);
|
2018-01-07 11:31:20 +00:00
|
|
|
} else {
|
|
|
|
Xbyak::Reg64 to_store = ctx.reg_alloc.UseGpr(args[0]);
|
2018-02-03 14:28:57 +00:00
|
|
|
code.mov(addr, to_store);
|
2018-01-07 11:31:20 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-02-20 17:38:29 +00:00
|
|
|
static void SetFPCRImpl(A64JitState* jit_state, u32 value) {
|
|
|
|
jit_state->SetFpcr(value);
|
|
|
|
}
|
|
|
|
|
|
|
|
void A64EmitX64::EmitA64SetFPCR(A64EmitContext& ctx, IR::Inst* inst) {
|
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
|
|
ctx.reg_alloc.HostCall(nullptr, {}, args[0]);
|
|
|
|
code.mov(code.ABI_PARAM1, code.r15);
|
|
|
|
code.CallFunction(SetFPCRImpl);
|
|
|
|
code.ldmxcsr(code.dword[code.r15 + offsetof(A64JitState, guest_MXCSR)]);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void SetFPSRImpl(A64JitState* jit_state, u32 value) {
|
|
|
|
jit_state->SetFpsr(value);
|
|
|
|
}
|
|
|
|
|
|
|
|
void A64EmitX64::EmitA64SetFPSR(A64EmitContext& ctx, IR::Inst* inst) {
|
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
|
|
ctx.reg_alloc.HostCall(nullptr, {}, args[0]);
|
|
|
|
code.mov(code.ABI_PARAM1, code.r15);
|
|
|
|
code.CallFunction(SetFPSRImpl);
|
|
|
|
code.ldmxcsr(code.dword[code.r15 + offsetof(A64JitState, guest_MXCSR)]);
|
|
|
|
}
|
|
|
|
|
2018-01-07 13:56:32 +00:00
|
|
|
void A64EmitX64::EmitA64SetPC(A64EmitContext& ctx, IR::Inst* inst) {
|
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
|
|
auto addr = qword[r15 + offsetof(A64JitState, pc)];
|
2018-01-27 00:38:09 +00:00
|
|
|
if (args[0].FitsInImmediateS32()) {
|
2018-02-03 14:28:57 +00:00
|
|
|
code.mov(addr, args[0].GetImmediateS32());
|
2018-01-07 13:56:32 +00:00
|
|
|
} else if (args[0].IsInXmm()) {
|
|
|
|
Xbyak::Xmm to_store = ctx.reg_alloc.UseXmm(args[0]);
|
2018-02-03 14:28:57 +00:00
|
|
|
code.movq(addr, to_store);
|
2018-01-07 13:56:32 +00:00
|
|
|
} else {
|
|
|
|
Xbyak::Reg64 to_store = ctx.reg_alloc.UseGpr(args[0]);
|
2018-02-03 14:28:57 +00:00
|
|
|
code.mov(addr, to_store);
|
2018-01-07 13:56:32 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-01-08 22:03:03 +00:00
|
|
|
void A64EmitX64::EmitA64CallSupervisor(A64EmitContext& ctx, IR::Inst* inst) {
|
2018-01-13 18:00:39 +00:00
|
|
|
ctx.reg_alloc.HostCall(nullptr);
|
2018-01-08 22:03:03 +00:00
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
|
|
ASSERT(args[0].IsImmediate());
|
|
|
|
u32 imm = args[0].GetImmediateU32();
|
2018-02-09 15:58:16 +00:00
|
|
|
DEVIRT(conf.callbacks, &A64::UserCallbacks::CallSVC).EmitCall(code, [&](RegList param) {
|
|
|
|
code.mov(param[0], imm);
|
2018-01-08 22:03:03 +00:00
|
|
|
});
|
2018-06-05 13:05:41 +01:00
|
|
|
// The kernel would have to execute ERET to get here, which would clear exclusive state.
|
|
|
|
code.mov(code.byte[r15 + offsetof(A64JitState, exclusive_state)], u8(0));
|
2018-01-08 22:03:03 +00:00
|
|
|
}
|
|
|
|
|
2018-01-13 17:54:29 +00:00
|
|
|
void A64EmitX64::EmitA64ExceptionRaised(A64EmitContext& ctx, IR::Inst* inst) {
|
|
|
|
ctx.reg_alloc.HostCall(nullptr);
|
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
|
|
ASSERT(args[0].IsImmediate() && args[1].IsImmediate());
|
|
|
|
u64 pc = args[0].GetImmediateU64();
|
|
|
|
u64 exception = args[1].GetImmediateU64();
|
2018-02-09 15:58:16 +00:00
|
|
|
DEVIRT(conf.callbacks, &A64::UserCallbacks::ExceptionRaised).EmitCall(code, [&](RegList param) {
|
|
|
|
code.mov(param[0], pc);
|
|
|
|
code.mov(param[1], exception);
|
2018-01-13 17:54:29 +00:00
|
|
|
});
|
|
|
|
}
|
|
|
|
|
2018-02-11 22:53:46 +00:00
|
|
|
void A64EmitX64::EmitA64DataCacheOperationRaised(A64EmitContext& ctx, IR::Inst* inst) {
|
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
|
|
ctx.reg_alloc.HostCall(nullptr, args[0], args[1]);
|
|
|
|
DEVIRT(conf.callbacks, &A64::UserCallbacks::DataCacheOperationRaised).EmitCall(code);
|
|
|
|
}
|
|
|
|
|
2018-02-11 23:27:28 +00:00
|
|
|
void A64EmitX64::EmitA64DataSynchronizationBarrier(A64EmitContext&, IR::Inst*) {
|
|
|
|
code.mfence();
|
|
|
|
}
|
|
|
|
|
|
|
|
void A64EmitX64::EmitA64DataMemoryBarrier(A64EmitContext&, IR::Inst*) {
|
|
|
|
code.lfence();
|
|
|
|
}
|
|
|
|
|
2018-02-20 16:54:10 +00:00
|
|
|
void A64EmitX64::EmitA64GetCNTPCT(A64EmitContext& ctx, IR::Inst* inst) {
|
|
|
|
ctx.reg_alloc.HostCall(inst);
|
|
|
|
DEVIRT(conf.callbacks, &A64::UserCallbacks::GetCNTPCT).EmitCall(code);
|
|
|
|
}
|
|
|
|
|
2018-02-20 16:44:13 +00:00
|
|
|
void A64EmitX64::EmitA64GetCTR(A64EmitContext& ctx, IR::Inst* inst) {
|
|
|
|
Xbyak::Reg32 result = ctx.reg_alloc.ScratchGpr().cvt32();
|
|
|
|
code.mov(result, conf.ctr_el0);
|
|
|
|
ctx.reg_alloc.DefineValue(inst, result);
|
|
|
|
}
|
|
|
|
|
2018-02-12 00:06:44 +00:00
|
|
|
void A64EmitX64::EmitA64GetDCZID(A64EmitContext& ctx, IR::Inst* inst) {
|
|
|
|
Xbyak::Reg32 result = ctx.reg_alloc.ScratchGpr().cvt32();
|
|
|
|
code.mov(result, conf.dczid_el0);
|
|
|
|
ctx.reg_alloc.DefineValue(inst, result);
|
|
|
|
}
|
|
|
|
|
2018-02-20 17:56:20 +00:00
|
|
|
void A64EmitX64::EmitA64GetTPIDR(A64EmitContext& ctx, IR::Inst* inst) {
|
|
|
|
Xbyak::Reg64 result = ctx.reg_alloc.ScratchGpr();
|
|
|
|
if (conf.tpidr_el0) {
|
|
|
|
code.mov(result, u64(conf.tpidr_el0));
|
|
|
|
code.mov(result, qword[result]);
|
|
|
|
} else {
|
|
|
|
code.xor_(result.cvt32(), result.cvt32());
|
|
|
|
}
|
|
|
|
ctx.reg_alloc.DefineValue(inst, result);
|
|
|
|
}
|
|
|
|
|
|
|
|
void A64EmitX64::EmitA64SetTPIDR(A64EmitContext& ctx, IR::Inst* inst) {
|
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
|
|
Xbyak::Reg64 value = ctx.reg_alloc.UseGpr(args[0]);
|
|
|
|
Xbyak::Reg64 addr = ctx.reg_alloc.ScratchGpr();
|
|
|
|
if (conf.tpidr_el0) {
|
|
|
|
code.mov(addr, u64(conf.tpidr_el0));
|
|
|
|
code.mov(qword[addr], value);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-02-12 00:06:44 +00:00
|
|
|
void A64EmitX64::EmitA64GetTPIDRRO(A64EmitContext& ctx, IR::Inst* inst) {
|
|
|
|
Xbyak::Reg64 result = ctx.reg_alloc.ScratchGpr();
|
|
|
|
if (conf.tpidrro_el0) {
|
|
|
|
code.mov(result, u64(conf.tpidrro_el0));
|
|
|
|
code.mov(result, qword[result]);
|
|
|
|
} else {
|
|
|
|
code.xor_(result.cvt32(), result.cvt32());
|
|
|
|
}
|
|
|
|
ctx.reg_alloc.DefineValue(inst, result);
|
|
|
|
}
|
|
|
|
|
A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR
2018-02-13 00:19:04 +00:00
|
|
|
void A64EmitX64::EmitA64ClearExclusive(A64EmitContext&, IR::Inst*) {
|
|
|
|
code.mov(code.byte[r15 + offsetof(A64JitState, exclusive_state)], u8(0));
|
|
|
|
}
|
|
|
|
|
|
|
|
void A64EmitX64::EmitA64SetExclusive(A64EmitContext& ctx, IR::Inst* inst) {
|
2018-06-05 12:27:37 +01:00
|
|
|
if (conf.global_monitor) {
|
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
|
|
ctx.reg_alloc.HostCall(nullptr, {}, args[0], args[1]);
|
|
|
|
|
|
|
|
code.mov(code.byte[r15 + offsetof(A64JitState, exclusive_state)], u8(1));
|
|
|
|
code.mov(code.ABI_PARAM1, reinterpret_cast<u64>(&conf));
|
|
|
|
code.CallFunction(static_cast<void(*)(A64::UserConfig&, u64, u8)>(
|
|
|
|
[](A64::UserConfig& conf, u64 vaddr, u8 size) {
|
|
|
|
conf.global_monitor->Mark(conf.processor_id, vaddr, size);
|
|
|
|
}
|
|
|
|
));
|
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR
2018-02-13 00:19:04 +00:00
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
|
|
ASSERT(args[1].IsImmediate());
|
2018-02-13 14:02:59 +00:00
|
|
|
Xbyak::Reg64 address = ctx.reg_alloc.UseGpr(args[0]);
|
A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR
2018-02-13 00:19:04 +00:00
|
|
|
|
|
|
|
code.mov(code.byte[r15 + offsetof(A64JitState, exclusive_state)], u8(1));
|
2018-02-13 14:02:59 +00:00
|
|
|
code.mov(qword[r15 + offsetof(A64JitState, exclusive_address)], address);
|
A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR
2018-02-13 00:19:04 +00:00
|
|
|
}
|
|
|
|
|
2018-02-18 13:00:41 +00:00
|
|
|
static Xbyak::RegExp EmitVAddrLookup(BlockOfCode& code, A64EmitContext& ctx, Xbyak::Label& abort, Xbyak::Reg64 vaddr, boost::optional<Xbyak::Reg64> arg_scratch = {}) {
|
2018-02-12 20:49:52 +00:00
|
|
|
constexpr size_t PAGE_BITS = 12;
|
|
|
|
constexpr size_t PAGE_SIZE = 1 << PAGE_BITS;
|
2018-02-18 13:00:41 +00:00
|
|
|
const size_t valid_page_index_bits = ctx.conf.page_table_address_space_bits - PAGE_BITS;
|
|
|
|
const size_t unused_top_bits = 64 - ctx.conf.page_table_address_space_bits;
|
2018-02-12 19:49:56 +00:00
|
|
|
|
|
|
|
Xbyak::Reg64 page_table = arg_scratch.value_or_eval([&]{ return ctx.reg_alloc.ScratchGpr(); });
|
|
|
|
Xbyak::Reg64 tmp = ctx.reg_alloc.ScratchGpr();
|
2018-02-18 13:00:41 +00:00
|
|
|
code.mov(page_table, reinterpret_cast<u64>(ctx.conf.page_table));
|
2018-02-12 19:49:56 +00:00
|
|
|
code.mov(tmp, vaddr);
|
2018-02-12 20:49:52 +00:00
|
|
|
if (unused_top_bits == 0) {
|
|
|
|
code.shr(tmp, int(PAGE_BITS));
|
2018-02-18 13:00:41 +00:00
|
|
|
} else if (ctx.conf.silently_mirror_page_table) {
|
2018-02-12 20:49:52 +00:00
|
|
|
if (valid_page_index_bits >= 32) {
|
|
|
|
code.shl(tmp, int(unused_top_bits));
|
|
|
|
code.shr(tmp, int(unused_top_bits + PAGE_BITS));
|
|
|
|
} else {
|
|
|
|
code.shr(tmp, int(PAGE_BITS));
|
|
|
|
code.and_(tmp, u32((1 << valid_page_index_bits) - 1));
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
ASSERT(valid_page_index_bits < 32);
|
|
|
|
code.shr(tmp, int(PAGE_BITS));
|
|
|
|
code.test(tmp, u32(-(1 << valid_page_index_bits)));
|
|
|
|
code.jnz(abort, code.T_NEAR);
|
|
|
|
}
|
2018-02-12 19:49:56 +00:00
|
|
|
code.mov(page_table, qword[page_table + tmp * sizeof(void*)]);
|
2018-02-12 20:49:52 +00:00
|
|
|
code.test(page_table, page_table);
|
|
|
|
code.jz(abort, code.T_NEAR);
|
2018-02-12 19:49:56 +00:00
|
|
|
code.mov(tmp, vaddr);
|
2018-02-12 20:49:52 +00:00
|
|
|
code.and_(tmp, static_cast<u32>(PAGE_SIZE - 1));
|
|
|
|
return page_table + tmp;
|
2018-02-12 19:49:56 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void A64EmitX64::EmitDirectPageTableMemoryRead(A64EmitContext& ctx, IR::Inst* inst, size_t bitsize) {
|
|
|
|
Xbyak::Label abort, end;
|
|
|
|
|
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
|
|
Xbyak::Reg64 vaddr = ctx.reg_alloc.UseGpr(args[0]);
|
|
|
|
Xbyak::Reg64 value = ctx.reg_alloc.ScratchGpr();
|
|
|
|
|
2018-02-18 13:00:41 +00:00
|
|
|
auto src_ptr = EmitVAddrLookup(code, ctx, abort, vaddr, value);
|
2018-02-12 19:49:56 +00:00
|
|
|
switch (bitsize) {
|
|
|
|
case 8:
|
|
|
|
code.movzx(value.cvt32(), code.byte[src_ptr]);
|
|
|
|
break;
|
|
|
|
case 16:
|
|
|
|
code.movzx(value.cvt32(), word[src_ptr]);
|
|
|
|
break;
|
|
|
|
case 32:
|
|
|
|
code.mov(value.cvt32(), dword[src_ptr]);
|
|
|
|
break;
|
|
|
|
case 64:
|
|
|
|
code.mov(value, qword[src_ptr]);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
code.L(end);
|
|
|
|
|
|
|
|
code.SwitchToFarCode();
|
|
|
|
code.L(abort);
|
|
|
|
code.call(read_fallbacks[std::make_tuple(bitsize, vaddr.getIdx(), value.getIdx())]);
|
|
|
|
code.jmp(end, code.T_NEAR);
|
|
|
|
code.SwitchToNearCode();
|
|
|
|
|
|
|
|
ctx.reg_alloc.DefineValue(inst, value);
|
|
|
|
}
|
|
|
|
|
|
|
|
void A64EmitX64::EmitDirectPageTableMemoryWrite(A64EmitContext& ctx, IR::Inst* inst, size_t bitsize) {
|
|
|
|
Xbyak::Label abort, end;
|
|
|
|
|
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
|
|
Xbyak::Reg64 vaddr = ctx.reg_alloc.UseGpr(args[0]);
|
|
|
|
Xbyak::Reg64 value = ctx.reg_alloc.UseGpr(args[1]);
|
|
|
|
|
2018-02-18 13:00:41 +00:00
|
|
|
auto dest_ptr = EmitVAddrLookup(code, ctx, abort, vaddr);
|
2018-02-12 19:49:56 +00:00
|
|
|
switch (bitsize) {
|
|
|
|
case 8:
|
|
|
|
code.mov(code.byte[dest_ptr], value.cvt8());
|
|
|
|
break;
|
|
|
|
case 16:
|
|
|
|
code.mov(word[dest_ptr], value.cvt16());
|
|
|
|
break;
|
|
|
|
case 32:
|
|
|
|
code.mov(dword[dest_ptr], value.cvt32());
|
|
|
|
break;
|
|
|
|
case 64:
|
|
|
|
code.mov(qword[dest_ptr], value);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
code.L(end);
|
|
|
|
|
|
|
|
code.SwitchToFarCode();
|
|
|
|
code.L(abort);
|
|
|
|
code.call(write_fallbacks[std::make_tuple(bitsize, vaddr.getIdx(), value.getIdx())]);
|
|
|
|
code.jmp(end, code.T_NEAR);
|
|
|
|
code.SwitchToNearCode();
|
|
|
|
}
|
|
|
|
|
2018-01-10 01:13:23 +00:00
|
|
|
void A64EmitX64::EmitA64ReadMemory8(A64EmitContext& ctx, IR::Inst* inst) {
|
2018-02-12 19:49:56 +00:00
|
|
|
if (conf.page_table) {
|
|
|
|
EmitDirectPageTableMemoryRead(ctx, inst, 8);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2018-02-09 15:58:16 +00:00
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
|
|
ctx.reg_alloc.HostCall(inst, {}, args[0]);
|
|
|
|
DEVIRT(conf.callbacks, &A64::UserCallbacks::MemoryRead8).EmitCall(code);
|
2018-01-10 01:13:23 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void A64EmitX64::EmitA64ReadMemory16(A64EmitContext& ctx, IR::Inst* inst) {
|
2018-02-12 19:49:56 +00:00
|
|
|
if (conf.page_table) {
|
|
|
|
EmitDirectPageTableMemoryRead(ctx, inst, 16);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2018-02-09 15:58:16 +00:00
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
|
|
ctx.reg_alloc.HostCall(inst, {}, args[0]);
|
|
|
|
DEVIRT(conf.callbacks, &A64::UserCallbacks::MemoryRead16).EmitCall(code);
|
2018-01-10 01:13:23 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void A64EmitX64::EmitA64ReadMemory32(A64EmitContext& ctx, IR::Inst* inst) {
|
2018-02-12 19:49:56 +00:00
|
|
|
if (conf.page_table) {
|
|
|
|
EmitDirectPageTableMemoryRead(ctx, inst, 32);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2018-02-09 15:58:16 +00:00
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
|
|
ctx.reg_alloc.HostCall(inst, {}, args[0]);
|
|
|
|
DEVIRT(conf.callbacks, &A64::UserCallbacks::MemoryRead32).EmitCall(code);
|
2018-01-10 01:13:23 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void A64EmitX64::EmitA64ReadMemory64(A64EmitContext& ctx, IR::Inst* inst) {
|
2018-02-12 19:49:56 +00:00
|
|
|
if (conf.page_table) {
|
|
|
|
EmitDirectPageTableMemoryRead(ctx, inst, 64);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2018-02-09 15:58:16 +00:00
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
|
|
ctx.reg_alloc.HostCall(inst, {}, args[0]);
|
|
|
|
DEVIRT(conf.callbacks, &A64::UserCallbacks::MemoryRead64).EmitCall(code);
|
2018-01-10 01:13:23 +00:00
|
|
|
}
|
|
|
|
|
2018-01-24 15:55:59 +00:00
|
|
|
void A64EmitX64::EmitA64ReadMemory128(A64EmitContext& ctx, IR::Inst* inst) {
|
2018-02-12 19:49:56 +00:00
|
|
|
if (conf.page_table) {
|
|
|
|
Xbyak::Label abort, end;
|
|
|
|
|
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
|
|
Xbyak::Reg64 vaddr = ctx.reg_alloc.UseGpr(args[0]);
|
|
|
|
Xbyak::Xmm value = ctx.reg_alloc.ScratchXmm();
|
|
|
|
|
2018-02-18 13:00:41 +00:00
|
|
|
auto src_ptr = EmitVAddrLookup(code, ctx, abort, vaddr);
|
2018-02-12 20:49:52 +00:00
|
|
|
code.movups(value, xword[src_ptr]);
|
2018-02-12 19:49:56 +00:00
|
|
|
code.L(end);
|
|
|
|
|
|
|
|
code.SwitchToFarCode();
|
|
|
|
code.L(abort);
|
|
|
|
code.call(read_fallbacks[std::make_tuple(128, vaddr.getIdx(), value.getIdx())]);
|
|
|
|
code.jmp(end, code.T_NEAR);
|
|
|
|
code.SwitchToNearCode();
|
|
|
|
|
|
|
|
ctx.reg_alloc.DefineValue(inst, value);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2018-02-09 15:58:16 +00:00
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
|
|
ctx.reg_alloc.HostCall(nullptr, {}, args[0]);
|
2018-02-12 18:18:47 +00:00
|
|
|
code.CallFunction(memory_read_128);
|
|
|
|
ctx.reg_alloc.DefineValue(inst, xmm0);
|
2018-01-24 15:55:59 +00:00
|
|
|
}
|
|
|
|
|
2018-01-10 01:13:23 +00:00
|
|
|
void A64EmitX64::EmitA64WriteMemory8(A64EmitContext& ctx, IR::Inst* inst) {
|
2018-02-12 19:49:56 +00:00
|
|
|
if (conf.page_table) {
|
|
|
|
EmitDirectPageTableMemoryWrite(ctx, inst, 8);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2018-02-09 15:58:16 +00:00
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
|
|
ctx.reg_alloc.HostCall(nullptr, {}, args[0], args[1]);
|
|
|
|
DEVIRT(conf.callbacks, &A64::UserCallbacks::MemoryWrite8).EmitCall(code);
|
2018-01-10 01:13:23 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void A64EmitX64::EmitA64WriteMemory16(A64EmitContext& ctx, IR::Inst* inst) {
|
2018-02-12 19:49:56 +00:00
|
|
|
if (conf.page_table) {
|
|
|
|
EmitDirectPageTableMemoryWrite(ctx, inst, 16);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2018-02-09 15:58:16 +00:00
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
|
|
ctx.reg_alloc.HostCall(nullptr, {}, args[0], args[1]);
|
|
|
|
DEVIRT(conf.callbacks, &A64::UserCallbacks::MemoryWrite16).EmitCall(code);
|
2018-01-10 01:13:23 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void A64EmitX64::EmitA64WriteMemory32(A64EmitContext& ctx, IR::Inst* inst) {
|
2018-02-12 19:49:56 +00:00
|
|
|
if (conf.page_table) {
|
|
|
|
EmitDirectPageTableMemoryWrite(ctx, inst, 32);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2018-02-09 15:58:16 +00:00
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
|
|
ctx.reg_alloc.HostCall(nullptr, {}, args[0], args[1]);
|
|
|
|
DEVIRT(conf.callbacks, &A64::UserCallbacks::MemoryWrite32).EmitCall(code);
|
2018-01-10 01:13:23 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void A64EmitX64::EmitA64WriteMemory64(A64EmitContext& ctx, IR::Inst* inst) {
|
2018-02-12 19:49:56 +00:00
|
|
|
if (conf.page_table) {
|
|
|
|
EmitDirectPageTableMemoryWrite(ctx, inst, 64);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2018-02-09 15:58:16 +00:00
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
|
|
ctx.reg_alloc.HostCall(nullptr, {}, args[0], args[1]);
|
|
|
|
DEVIRT(conf.callbacks, &A64::UserCallbacks::MemoryWrite64).EmitCall(code);
|
2018-01-10 01:13:23 +00:00
|
|
|
}
|
|
|
|
|
2018-01-24 15:55:59 +00:00
|
|
|
void A64EmitX64::EmitA64WriteMemory128(A64EmitContext& ctx, IR::Inst* inst) {
|
2018-02-12 19:49:56 +00:00
|
|
|
if (conf.page_table) {
|
|
|
|
Xbyak::Label abort, end;
|
|
|
|
|
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
|
|
Xbyak::Reg64 vaddr = ctx.reg_alloc.UseGpr(args[0]);
|
|
|
|
Xbyak::Xmm value = ctx.reg_alloc.UseXmm(args[1]);
|
|
|
|
|
2018-02-18 13:00:41 +00:00
|
|
|
auto dest_ptr = EmitVAddrLookup(code, ctx, abort, vaddr);
|
2018-02-12 19:49:56 +00:00
|
|
|
code.movups(xword[dest_ptr], value);
|
|
|
|
code.L(end);
|
|
|
|
|
|
|
|
code.SwitchToFarCode();
|
|
|
|
code.L(abort);
|
|
|
|
code.call(write_fallbacks[std::make_tuple(128, vaddr.getIdx(), value.getIdx())]);
|
|
|
|
code.jmp(end, code.T_NEAR);
|
|
|
|
code.SwitchToNearCode();
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2018-02-09 15:58:16 +00:00
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
|
|
ctx.reg_alloc.Use(args[0], ABI_PARAM2);
|
2018-02-12 18:18:47 +00:00
|
|
|
ctx.reg_alloc.Use(args[1], HostLoc::XMM0);
|
2018-02-09 15:58:16 +00:00
|
|
|
ctx.reg_alloc.EndOfAllocScope();
|
|
|
|
ctx.reg_alloc.HostCall(nullptr);
|
2018-02-12 18:18:47 +00:00
|
|
|
code.CallFunction(memory_write_128);
|
2018-01-24 15:55:59 +00:00
|
|
|
}
|
|
|
|
|
2018-06-05 12:26:05 +01:00
|
|
|
void A64EmitX64::EmitExclusiveWrite(A64EmitContext& ctx, IR::Inst* inst, size_t bitsize) {
|
2018-06-05 12:27:37 +01:00
|
|
|
if (conf.global_monitor) {
|
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
|
|
|
|
|
|
if (bitsize != 128) {
|
|
|
|
ctx.reg_alloc.HostCall(inst, {}, args[0], args[1]);
|
|
|
|
} else {
|
|
|
|
ctx.reg_alloc.Use(args[0], ABI_PARAM2);
|
|
|
|
ctx.reg_alloc.Use(args[1], HostLoc::XMM0);
|
|
|
|
ctx.reg_alloc.EndOfAllocScope();
|
|
|
|
ctx.reg_alloc.HostCall(inst);
|
|
|
|
}
|
|
|
|
|
|
|
|
Xbyak::Label end;
|
|
|
|
|
|
|
|
code.mov(code.ABI_RETURN, u32(1));
|
|
|
|
code.cmp(code.byte[r15 + offsetof(A64JitState, exclusive_state)], u8(0));
|
|
|
|
code.je(end);
|
|
|
|
code.mov(code.ABI_PARAM1, reinterpret_cast<u64>(&conf));
|
|
|
|
switch (bitsize) {
|
|
|
|
case 8:
|
|
|
|
code.CallFunction(static_cast<u32(*)(A64::UserConfig&, u64, u8)>(
|
|
|
|
[](A64::UserConfig& conf, u64 vaddr, u8 value) -> u32 {
|
|
|
|
return conf.global_monitor->DoExclusiveOperation(conf.processor_id, vaddr, 1, [&]{
|
|
|
|
conf.callbacks->MemoryWrite8(vaddr, value);
|
|
|
|
}) ? 0 : 1;
|
|
|
|
}
|
|
|
|
));
|
|
|
|
break;
|
|
|
|
case 16:
|
|
|
|
code.CallFunction(static_cast<u32(*)(A64::UserConfig&, u64, u16)>(
|
|
|
|
[](A64::UserConfig& conf, u64 vaddr, u16 value) -> u32 {
|
|
|
|
return conf.global_monitor->DoExclusiveOperation(conf.processor_id, vaddr, 2, [&]{
|
|
|
|
conf.callbacks->MemoryWrite16(vaddr, value);
|
|
|
|
}) ? 0 : 1;
|
|
|
|
}
|
|
|
|
));
|
|
|
|
break;
|
|
|
|
case 32:
|
|
|
|
code.CallFunction(static_cast<u32(*)(A64::UserConfig&, u64, u32)>(
|
|
|
|
[](A64::UserConfig& conf, u64 vaddr, u32 value) -> u32 {
|
|
|
|
return conf.global_monitor->DoExclusiveOperation(conf.processor_id, vaddr, 4, [&]{
|
|
|
|
conf.callbacks->MemoryWrite32(vaddr, value);
|
|
|
|
}) ? 0 : 1;
|
|
|
|
}
|
|
|
|
));
|
|
|
|
break;
|
|
|
|
case 64:
|
|
|
|
code.CallFunction(static_cast<u32(*)(A64::UserConfig&, u64, u64)>(
|
|
|
|
[](A64::UserConfig& conf, u64 vaddr, u64 value) -> u32 {
|
|
|
|
return conf.global_monitor->DoExclusiveOperation(conf.processor_id, vaddr, 8, [&]{
|
|
|
|
conf.callbacks->MemoryWrite64(vaddr, value);
|
|
|
|
}) ? 0 : 1;
|
|
|
|
}
|
|
|
|
));
|
|
|
|
break;
|
|
|
|
case 128:
|
|
|
|
code.sub(rsp, 8 + 16 + ABI_SHADOW_SPACE);
|
|
|
|
code.lea(code.ABI_PARAM3, ptr[rsp + ABI_SHADOW_SPACE]);
|
|
|
|
code.movaps(xword[code.ABI_PARAM3], xmm0);
|
|
|
|
code.CallFunction(static_cast<u32(*)(A64::UserConfig&, u64, A64::Vector&)>(
|
|
|
|
[](A64::UserConfig& conf, u64 vaddr, A64::Vector& value) -> u32 {
|
|
|
|
return conf.global_monitor->DoExclusiveOperation(conf.processor_id, vaddr, 16, [&]{
|
|
|
|
conf.callbacks->MemoryWrite128(vaddr, value);
|
|
|
|
}) ? 0 : 1;
|
|
|
|
}
|
|
|
|
));
|
|
|
|
code.add(rsp, 8 + 16 + ABI_SHADOW_SPACE);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
UNREACHABLE();
|
|
|
|
}
|
|
|
|
code.L(end);
|
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2018-06-05 12:26:05 +01:00
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
|
|
Xbyak::Reg64 vaddr = ctx.reg_alloc.UseGpr(args[0]);
|
|
|
|
int value_idx = bitsize != 128
|
|
|
|
? ctx.reg_alloc.UseGpr(args[1]).getIdx()
|
|
|
|
: ctx.reg_alloc.UseXmm(args[1]).getIdx();
|
|
|
|
|
A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR
2018-02-13 00:19:04 +00:00
|
|
|
Xbyak::Label end;
|
|
|
|
Xbyak::Reg32 passed = ctx.reg_alloc.ScratchGpr().cvt32();
|
2018-02-13 14:02:59 +00:00
|
|
|
Xbyak::Reg64 tmp = ctx.reg_alloc.ScratchGpr();
|
A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR
2018-02-13 00:19:04 +00:00
|
|
|
|
|
|
|
code.mov(passed, u32(1));
|
|
|
|
code.cmp(code.byte[r15 + offsetof(A64JitState, exclusive_state)], u8(0));
|
|
|
|
code.je(end);
|
|
|
|
code.mov(tmp, vaddr);
|
2018-02-13 14:02:59 +00:00
|
|
|
code.xor_(tmp, qword[r15 + offsetof(A64JitState, exclusive_address)]);
|
|
|
|
code.test(tmp, static_cast<u32>(A64JitState::RESERVATION_GRANULE_MASK & 0xFFFF'FFFF));
|
A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR
2018-02-13 00:19:04 +00:00
|
|
|
code.jne(end);
|
|
|
|
code.mov(code.byte[r15 + offsetof(A64JitState, exclusive_state)], u8(0));
|
|
|
|
code.call(write_fallbacks[std::make_tuple(bitsize, vaddr.getIdx(), value_idx)]);
|
|
|
|
code.xor_(passed, passed);
|
|
|
|
code.L(end);
|
|
|
|
|
|
|
|
ctx.reg_alloc.DefineValue(inst, passed);
|
|
|
|
}
|
|
|
|
|
|
|
|
void A64EmitX64::EmitA64ExclusiveWriteMemory8(A64EmitContext& ctx, IR::Inst* inst) {
|
2018-06-05 12:26:05 +01:00
|
|
|
EmitExclusiveWrite(ctx, inst, 8);
|
A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR
2018-02-13 00:19:04 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void A64EmitX64::EmitA64ExclusiveWriteMemory16(A64EmitContext& ctx, IR::Inst* inst) {
|
2018-06-05 12:26:05 +01:00
|
|
|
EmitExclusiveWrite(ctx, inst, 16);
|
A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR
2018-02-13 00:19:04 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void A64EmitX64::EmitA64ExclusiveWriteMemory32(A64EmitContext& ctx, IR::Inst* inst) {
|
2018-06-05 12:26:05 +01:00
|
|
|
EmitExclusiveWrite(ctx, inst, 32);
|
A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR
2018-02-13 00:19:04 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void A64EmitX64::EmitA64ExclusiveWriteMemory64(A64EmitContext& ctx, IR::Inst* inst) {
|
2018-06-05 12:26:05 +01:00
|
|
|
EmitExclusiveWrite(ctx, inst, 64);
|
A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR
2018-02-13 00:19:04 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void A64EmitX64::EmitA64ExclusiveWriteMemory128(A64EmitContext& ctx, IR::Inst* inst) {
|
2018-06-05 12:26:05 +01:00
|
|
|
EmitExclusiveWrite(ctx, inst, 128);
|
A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR
2018-02-13 00:19:04 +00:00
|
|
|
}
|
|
|
|
|
2018-01-06 21:15:25 +00:00
|
|
|
void A64EmitX64::EmitTerminalImpl(IR::Term::Interpret terminal, IR::LocationDescriptor) {
|
2018-02-03 14:28:57 +00:00
|
|
|
code.SwitchMxcsrOnExit();
|
2018-02-09 15:58:16 +00:00
|
|
|
DEVIRT(conf.callbacks, &A64::UserCallbacks::InterpreterFallback).EmitCall(code, [&](RegList param) {
|
|
|
|
code.mov(param[0], A64::LocationDescriptor{terminal.next}.PC());
|
|
|
|
code.mov(qword[r15 + offsetof(A64JitState, pc)], param[0]);
|
|
|
|
code.mov(param[1].cvt32(), terminal.num_instructions);
|
2018-01-08 18:33:42 +00:00
|
|
|
});
|
2018-02-03 14:28:57 +00:00
|
|
|
code.ReturnFromRunCode(true); // TODO: Check cycles
|
2018-01-06 21:15:25 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void A64EmitX64::EmitTerminalImpl(IR::Term::ReturnToDispatch, IR::LocationDescriptor) {
|
2018-02-03 14:28:57 +00:00
|
|
|
code.ReturnFromRunCode();
|
2018-01-06 21:15:25 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void A64EmitX64::EmitTerminalImpl(IR::Term::LinkBlock terminal, IR::LocationDescriptor) {
|
2018-02-03 14:28:57 +00:00
|
|
|
code.cmp(qword[r15 + offsetof(A64JitState, cycles_remaining)], 0);
|
2018-01-06 21:15:25 +00:00
|
|
|
|
2018-02-03 14:28:57 +00:00
|
|
|
patch_information[terminal.next].jg.emplace_back(code.getCurr());
|
2018-01-06 21:15:25 +00:00
|
|
|
if (auto next_bb = GetBasicBlock(terminal.next)) {
|
|
|
|
EmitPatchJg(terminal.next, next_bb->entrypoint);
|
|
|
|
} else {
|
|
|
|
EmitPatchJg(terminal.next);
|
|
|
|
}
|
2018-02-03 14:28:57 +00:00
|
|
|
code.mov(rax, A64::LocationDescriptor{terminal.next}.PC());
|
|
|
|
code.mov(qword[r15 + offsetof(A64JitState, pc)], rax);
|
|
|
|
code.ForceReturnFromRunCode();
|
2018-01-06 21:15:25 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void A64EmitX64::EmitTerminalImpl(IR::Term::LinkBlockFast terminal, IR::LocationDescriptor) {
|
2018-02-03 14:28:57 +00:00
|
|
|
patch_information[terminal.next].jmp.emplace_back(code.getCurr());
|
2018-01-06 21:15:25 +00:00
|
|
|
if (auto next_bb = GetBasicBlock(terminal.next)) {
|
|
|
|
EmitPatchJmp(terminal.next, next_bb->entrypoint);
|
|
|
|
} else {
|
|
|
|
EmitPatchJmp(terminal.next);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-01-27 22:44:17 +00:00
|
|
|
void A64EmitX64::EmitTerminalImpl(IR::Term::PopRSBHint, IR::LocationDescriptor) {
|
|
|
|
// This calculation has to match up with A64::LocationDescriptor::UniqueHash
|
|
|
|
// TODO: Optimization is available here based on known state of FPSCR_mode and CPSR_et.
|
2018-02-03 14:28:57 +00:00
|
|
|
code.mov(rcx, qword[r15 + offsetof(A64JitState, pc)]);
|
|
|
|
code.mov(ebx, dword[r15 + offsetof(A64JitState, fpcr)]);
|
|
|
|
code.and_(ebx, A64::LocationDescriptor::FPCR_MASK);
|
|
|
|
code.shl(ebx, 37);
|
|
|
|
code.or_(rbx, rcx);
|
|
|
|
|
|
|
|
code.mov(eax, dword[r15 + offsetof(A64JitState, rsb_ptr)]);
|
|
|
|
code.sub(eax, 1);
|
|
|
|
code.and_(eax, u32(A64JitState::RSBPtrMask));
|
|
|
|
code.mov(dword[r15 + offsetof(A64JitState, rsb_ptr)], eax);
|
|
|
|
code.cmp(rbx, qword[r15 + offsetof(A64JitState, rsb_location_descriptors) + rax * sizeof(u64)]);
|
|
|
|
code.jne(code.GetReturnFromRunCodeAddress());
|
|
|
|
code.mov(rax, qword[r15 + offsetof(A64JitState, rsb_codeptrs) + rax * sizeof(u64)]);
|
|
|
|
code.jmp(rax);
|
2018-01-06 21:15:25 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void A64EmitX64::EmitTerminalImpl(IR::Term::If terminal, IR::LocationDescriptor initial_location) {
|
2018-01-17 00:34:33 +00:00
|
|
|
switch (terminal.if_) {
|
|
|
|
case IR::Cond::AL:
|
|
|
|
case IR::Cond::NV:
|
|
|
|
EmitTerminal(terminal.then_, initial_location);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
Xbyak::Label pass = EmitCond(terminal.if_);
|
|
|
|
EmitTerminal(terminal.else_, initial_location);
|
2018-02-03 14:28:57 +00:00
|
|
|
code.L(pass);
|
2018-01-17 00:34:33 +00:00
|
|
|
EmitTerminal(terminal.then_, initial_location);
|
|
|
|
break;
|
|
|
|
}
|
2018-01-06 21:15:25 +00:00
|
|
|
}
|
|
|
|
|
2018-01-07 16:33:02 +00:00
|
|
|
void A64EmitX64::EmitTerminalImpl(IR::Term::CheckBit terminal, IR::LocationDescriptor initial_location) {
|
|
|
|
Xbyak::Label fail;
|
2018-02-03 14:28:57 +00:00
|
|
|
code.cmp(code.byte[r15 + offsetof(A64JitState, check_bit)], u8(0));
|
|
|
|
code.jz(fail);
|
2018-01-07 16:33:02 +00:00
|
|
|
EmitTerminal(terminal.then_, initial_location);
|
2018-02-03 14:28:57 +00:00
|
|
|
code.L(fail);
|
2018-01-07 16:33:02 +00:00
|
|
|
EmitTerminal(terminal.else_, initial_location);
|
|
|
|
}
|
|
|
|
|
2018-01-06 21:15:25 +00:00
|
|
|
void A64EmitX64::EmitTerminalImpl(IR::Term::CheckHalt terminal, IR::LocationDescriptor initial_location) {
|
2018-02-03 14:28:57 +00:00
|
|
|
code.cmp(code.byte[r15 + offsetof(A64JitState, halt_requested)], u8(0));
|
|
|
|
code.jne(code.GetForceReturnFromRunCodeAddress());
|
2018-01-06 21:15:25 +00:00
|
|
|
EmitTerminal(terminal.else_, initial_location);
|
|
|
|
}
|
|
|
|
|
2018-01-07 00:11:57 +00:00
|
|
|
void A64EmitX64::EmitPatchJg(const IR::LocationDescriptor& target_desc, CodePtr target_code_ptr) {
|
2018-02-03 14:28:57 +00:00
|
|
|
const CodePtr patch_location = code.getCurr();
|
2018-01-06 21:15:25 +00:00
|
|
|
if (target_code_ptr) {
|
2018-02-03 14:28:57 +00:00
|
|
|
code.jg(target_code_ptr);
|
2018-01-06 21:15:25 +00:00
|
|
|
} else {
|
2018-02-03 14:28:57 +00:00
|
|
|
code.mov(rax, A64::LocationDescriptor{target_desc}.PC());
|
|
|
|
code.mov(qword[r15 + offsetof(A64JitState, pc)], rax);
|
|
|
|
code.jg(code.GetReturnFromRunCodeAddress());
|
2018-01-06 21:15:25 +00:00
|
|
|
}
|
2018-02-03 14:28:57 +00:00
|
|
|
code.EnsurePatchLocationSize(patch_location, 30); // TODO: Reduce size
|
2018-01-06 21:15:25 +00:00
|
|
|
}
|
|
|
|
|
2018-01-07 00:11:57 +00:00
|
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void A64EmitX64::EmitPatchJmp(const IR::LocationDescriptor& target_desc, CodePtr target_code_ptr) {
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2018-02-03 14:28:57 +00:00
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const CodePtr patch_location = code.getCurr();
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2018-01-06 21:15:25 +00:00
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if (target_code_ptr) {
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2018-02-03 14:28:57 +00:00
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code.jmp(target_code_ptr);
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2018-01-06 21:15:25 +00:00
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} else {
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2018-02-03 14:28:57 +00:00
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code.mov(rax, A64::LocationDescriptor{target_desc}.PC());
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code.mov(qword[r15 + offsetof(A64JitState, pc)], rax);
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code.jmp(code.GetReturnFromRunCodeAddress());
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2018-01-06 21:15:25 +00:00
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}
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2018-02-03 14:28:57 +00:00
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code.EnsurePatchLocationSize(patch_location, 30); // TODO: Reduce size
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2018-01-06 21:15:25 +00:00
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}
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void A64EmitX64::EmitPatchMovRcx(CodePtr target_code_ptr) {
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if (!target_code_ptr) {
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2018-02-03 14:28:57 +00:00
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target_code_ptr = code.GetReturnFromRunCodeAddress();
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2018-01-06 21:15:25 +00:00
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}
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2018-02-03 14:28:57 +00:00
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const CodePtr patch_location = code.getCurr();
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code.mov(code.rcx, reinterpret_cast<u64>(target_code_ptr));
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code.EnsurePatchLocationSize(patch_location, 10);
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2018-01-06 21:15:25 +00:00
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}
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2018-01-26 13:51:48 +00:00
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} // namespace Dynarmic::BackendX64
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